From a08765d2871b891c8da2e8686a0db35b320c96b0 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@google.com>
Date: Tue, 5 Feb 2019 14:03:44 -0800
Subject: [PATCH] mb/google/{hatch,sarien}: Configure GPIOs using
 cnl_configure_pads

This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.

BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.

Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/google/hatch/ramstage.c  |  3 ++-
 src/mainboard/google/sarien/ramstage.c | 14 ++------------
 2 files changed, 4 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c
index b8e80e744a..5824e66735 100644
--- a/src/mainboard/google/hatch/ramstage.c
+++ b/src/mainboard/google/hatch/ramstage.c
@@ -16,6 +16,7 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <ec/ec.h>
+#include <soc/gpio.h>
 #include <soc/ramstage.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -26,7 +27,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	size_t num_gpios;
 
 	gpio_table = variant_gpio_table(&num_gpios);
-	gpio_configure_pads(gpio_table, num_gpios);
+	cnl_configure_pads(gpio_table, num_gpios);
 }
 
 static void mainboard_enable(struct device *dev)
diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index c2dc27daee..96321f8d49 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/acpi.h>
+#include <soc/gpio.h>
 #include <soc/ramstage.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -24,22 +25,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	size_t num_gpios;
 
 	gpio_table = variant_gpio_table(&num_gpios);
-	gpio_configure_pads(gpio_table, num_gpios);
-}
-
-/* Workaround FSP issue by reprogramming GPIOs after FSP-S */
-static void mainboard_init(struct device *dev)
-{
-	const struct pad_config *gpio_table;
-	size_t num_gpios;
-
-	gpio_table = variant_gpio_table(&num_gpios);
-	gpio_configure_pads(gpio_table, num_gpios);
+	cnl_configure_pads(gpio_table, num_gpios);
 }
 
 static void mainboard_enable(struct device *dev)
 {
-	dev->ops->init = mainboard_init;
 	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }