soc/sifive/fu540: Load PLL settings from a struct
The different PLLs in the fu540 use the same register layout, so use one function (configure_pll) to program a PLL and wait for it to lock. This also makes it possible to dynamically calculate the PLL settings later. TEST=Boot until "Payload not loaded" on HiFive Unleashed Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/29356 Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan Neuschäfer
Patrick Georgi
parent
44d2c8541a
commit
a09c2e1624
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@ -20,6 +20,9 @@
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#include <stdlib.h>
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#include <stdint.h>
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// 33.33 Mhz after reset
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#define FU540_BASE_FQY 33330
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struct prci_ctlr {
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u32 hfxosccfg; /* offset 0x00 */
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u32 corepllcfg0; /* offset 0x04 */
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@ -40,33 +43,19 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
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#define PRCI_CORECLK_CORE_PLL 0
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#define PRCI_CORECLK_HFCLK 1
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#define PRCI_COREPLLCFG0_LOCK (1u << 31)
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#define PRCI_COREPLLCFG0_DIVR_SHIFT 0
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#define PRCI_COREPLLCFG0_DIVF_SHIFT 6
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#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_COREPLLCFG0_RANGE_SHIFT 18
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#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_COREPLLCFG0_FSE_SHIFT 25
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#define PRCI_COREPLLCFG0_DIVR_MASK (0x03f << PRCI_COREPLLCFG0_DIVR_SHIFT)
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#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
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#define PRCI_COREPLLCFG0_DIVQ_MASK (0x007 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
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#define PRCI_COREPLLCFG0_RANGE_MASK (0x07 << PRCI_COREPLLCFG0_RANGE_SHIFT)
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#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
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#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
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#define PRCI_DDRPLLCFG0_LOCK (1u << 31)
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#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
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#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
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#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
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#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
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#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
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#define PRCI_DDRPLLCFG0_FSE_SHIFT 25
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#define PRCI_DDRPLLCFG0_DIVR_MASK (0x03f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
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#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
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#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x007 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
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#define PRCI_DDRPLLCFG0_RANGE_MASK (0x07 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
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#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
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#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
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#define PRCI_PLLCFG_LOCK (1u << 31)
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#define PRCI_PLLCFG_DIVR_SHIFT 0
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#define PRCI_PLLCFG_DIVF_SHIFT 6
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#define PRCI_PLLCFG_DIVQ_SHIFT 15
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#define PRCI_PLLCFG_RANGE_SHIFT 18
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#define PRCI_PLLCFG_BYPASS_SHIFT 24
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#define PRCI_PLLCFG_FSE_SHIFT 25
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#define PRCI_PLLCFG_DIVR_MASK (0x03f << PRCI_PLLCFG_DIVR_SHIFT)
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#define PRCI_PLLCFG_DIVF_MASK (0x1ff << PRCI_PLLCFG_DIVF_SHIFT)
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#define PRCI_PLLCFG_DIVQ_MASK (0x007 << PRCI_PLLCFG_DIVQ_SHIFT)
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#define PRCI_PLLCFG_RANGE_MASK (0x07 << PRCI_PLLCFG_RANGE_SHIFT)
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#define PRCI_PLLCFG_BYPASS_MASK (0x1 << PRCI_PLLCFG_BYPASS_SHIFT)
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#define PRCI_PLLCFG_FSE_MASK (0x1 << PRCI_PLLCFG_FSE_SHIFT)
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#define PRCI_DDRPLLCFG1_MASK (1u << 31)
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@ -78,6 +67,38 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
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#define PRCI_DEVICESRESET_DDR_PHY_RST_N(x) (((x) & 0x1) << 3)
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#define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)
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/* Clock initialization should only be done in romstage. */
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#if ENV_ROMSTAGE
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struct pll_settings {
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unsigned int divr:6;
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unsigned int divf:9;
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unsigned int divq:3;
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unsigned int range:3;
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unsigned int bypass:1;
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unsigned int fse:1;
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};
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static void configure_pll(u32 *reg, const struct pll_settings *s)
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{
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// Write the settings to the register
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u32 c = read32(reg);
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clrsetbits_le32(&c, PRCI_PLLCFG_DIVR_MASK
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| PRCI_PLLCFG_DIVF_MASK | PRCI_PLLCFG_DIVQ_MASK
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| PRCI_PLLCFG_RANGE_MASK | PRCI_PLLCFG_BYPASS_MASK
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| PRCI_PLLCFG_FSE_MASK,
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(s->divr << PRCI_PLLCFG_DIVR_SHIFT)
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| (s->divf << PRCI_PLLCFG_DIVF_SHIFT)
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| (s->divq << PRCI_PLLCFG_DIVQ_SHIFT)
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| (s->range << PRCI_PLLCFG_RANGE_SHIFT)
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| (s->bypass << PRCI_PLLCFG_BYPASS_SHIFT)
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| (s->fse << PRCI_PLLCFG_FSE_SHIFT));
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write32(reg, c);
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// Wait for PLL lock
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while (!(read32(reg) & PRCI_PLLCFG_LOCK))
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; /* TODO: implement a timeout */
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}
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/*
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* Set coreclk according to the SiFive FU540-C000 Manual
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* https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
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@ -88,13 +109,14 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
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* For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1),
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* divf = 59 (4000 MHz VCO), divq = 2 (/4 Output divider)
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*/
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#define PRCI_CORECLK_DIVR 0
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#define PRCI_CORECLK_DIVF 59
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#define PRCI_CORECLK_DIVQ 2
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#define PRCI_CORECLK_RANGE 4
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#define PRCI_CORECLK_BYPASS 0
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#define PRCI_CORECLK_FSE 1
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static const struct pll_settings corepll_settings = {
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.divr = 0,
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.divf = 59,
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.divq = 2,
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.range = 4,
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.bypass = 0,
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.fse = 1,
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};
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/*
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* Section 7.4.3: DDR and Ethernet Subsystem Clocking and Reset
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@ -110,41 +132,22 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
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* GEMGXLPLL is set up for 125 MHz output frequency.
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* divr = 0, divf = 59 (4000 MHz VCO), divq = 5
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*/
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static const struct pll_settings ddrpll_settings = {
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.divr = 0,
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.divf = 55,
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.divq = 2,
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.range = 4,
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.bypass = 0,
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.fse = 1,
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};
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#define PRCI_DDRCLK_DIVR 0
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#define PRCI_DDRCLK_DIVF 55
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#define PRCI_DDRCLK_DIVQ 2
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#define PRCI_DDRCLK_RANGE 4
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#define PRCI_DDRCLK_BYPASS 0
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#define PRCI_DDRCLK_FSE 1
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// 33.33 Mhz after reset
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#define FU540_BASE_FQY 33330
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/* Clock initialization should only be done in romstage. */
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#if ENV_ROMSTAGE
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static void init_coreclk(void)
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{
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// switch coreclk to input reference frequency before modifying PLL
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clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK,
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PRCI_CORECLK_HFCLK);
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u32 c = read32(&prci->corepllcfg0);
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clrsetbits_le32(&c, PRCI_COREPLLCFG0_DIVR_MASK
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| PRCI_COREPLLCFG0_DIVF_MASK | PRCI_COREPLLCFG0_DIVQ_MASK
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| PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK
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| PRCI_COREPLLCFG0_FSE_MASK,
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(PRCI_CORECLK_DIVR << PRCI_COREPLLCFG0_DIVR_SHIFT)
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| (PRCI_CORECLK_DIVF << PRCI_COREPLLCFG0_DIVF_SHIFT)
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| (PRCI_CORECLK_DIVQ << PRCI_COREPLLCFG0_DIVQ_SHIFT)
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| (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT)
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| (PRCI_CORECLK_BYPASS << PRCI_COREPLLCFG0_BYPASS_SHIFT)
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| (PRCI_CORECLK_FSE << PRCI_COREPLLCFG0_FSE_SHIFT));
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write32(&prci->corepllcfg0, c);
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// wait for PLL lock
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while (!(read32(&prci->corepllcfg0) & PRCI_COREPLLCFG0_LOCK))
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; /* TODO: implement a timeout */
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configure_pll(&prci->corepllcfg0, &corepll_settings);
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// switch coreclk to use corepll
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clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK,
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@ -158,22 +161,7 @@ static void init_pll_ddr(void)
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clrbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK);
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write32(&prci->ddrpllcfg1, cfg1);
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u32 c = read32(&prci->ddrpllcfg0);
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clrsetbits_le32(&c, PRCI_DDRPLLCFG0_DIVR_MASK
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| PRCI_DDRPLLCFG0_DIVF_MASK | PRCI_DDRPLLCFG0_DIVQ_MASK
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| PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK
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| PRCI_DDRPLLCFG0_FSE_MASK,
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(PRCI_DDRCLK_DIVR << PRCI_DDRPLLCFG0_DIVR_SHIFT)
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| (PRCI_DDRCLK_DIVF << PRCI_DDRPLLCFG0_DIVF_SHIFT)
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| (PRCI_DDRCLK_DIVQ << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
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| (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT)
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| (PRCI_DDRCLK_BYPASS << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
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| (PRCI_DDRCLK_FSE << PRCI_DDRPLLCFG0_FSE_SHIFT));
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write32(&prci->ddrpllcfg0, c);
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// wait for PLL lock
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while (!(read32(&prci->ddrpllcfg0) & PRCI_DDRPLLCFG0_LOCK))
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; /* TODO: implement a timeout */
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configure_pll(&prci->ddrpllcfg0, &ddrpll_settings);
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// enable ddr clock output
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setbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK);
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@ -249,12 +237,12 @@ int clock_get_coreclk_khz(void)
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return FU540_BASE_FQY;
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u32 cfg = read32(&prci->corepllcfg0);
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u32 divr = (cfg & PRCI_COREPLLCFG0_DIVR_MASK)
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>> PRCI_COREPLLCFG0_DIVR_SHIFT;
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u32 divf = (cfg & PRCI_COREPLLCFG0_DIVF_MASK)
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>> PRCI_COREPLLCFG0_DIVF_SHIFT;
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u32 divq = (cfg & PRCI_COREPLLCFG0_DIVQ_MASK)
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>> PRCI_COREPLLCFG0_DIVQ_SHIFT;
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u32 divr = (cfg & PRCI_PLLCFG_DIVR_MASK)
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>> PRCI_PLLCFG_DIVR_SHIFT;
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u32 divf = (cfg & PRCI_PLLCFG_DIVF_MASK)
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>> PRCI_PLLCFG_DIVF_SHIFT;
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u32 divq = (cfg & PRCI_PLLCFG_DIVQ_MASK)
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>> PRCI_PLLCFG_DIVQ_SHIFT;
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printk(BIOS_SPEW, "clk: r=%d f=%d q=%d\n", divr, divf, divq);
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return FU540_BASE_FQY
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