intel/cpu: rename car.h to romstage.h

This header has nothing to do with cache-as-ram. Therefore, 'car'
is the wrong term to use. It is about providing a prototype for
*romstage*.

Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6661
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/include/cpu/intel/car.h

@@ -1,7 +0,0 @@
-#ifndef _CPU_INTEL_CAR_H
-#define _CPU_INTEL_CAR_H
-
-/* std signature of entry-point to romstage.c */
-void main(unsigned long bist);
-
-#endif /* _CPU_INTEL_CAR_H */

src/include/cpu/intel/romstage.h

@@ -0,0 +1,7 @@
+#ifndef _CPU_INTEL_ROMSTAGE_H
+#define _CPU_INTEL_ROMSTAGE_H
+
+/* std signature of entry-point to romstage.c */
+void main(unsigned long bist);
+
+#endif /* _CPU_INTEL_ROMSTAGE_H */

src/mainboard/a-trend/atc-6220/romstage.c

@@ -42,7 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/a-trend/atc-6240/romstage.c

@@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/aaeon/pfm-540i_revb/romstage.c

@@ -54,7 +54,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/abit/be6-ii_v2_0/romstage.c

@@ -43,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/advantech/pcm-5820/romstage.c

@@ -30,7 +30,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/amd/db800/romstage.c

@@ -49,7 +49,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/amd/norwich/romstage.c

@@ -45,7 +45,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/amd/rumba/romstage.c

@@ -31,7 +31,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/geode_gx2/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {

src/mainboard/aopen/dxplplusu/romstage.c

@@ -39,7 +39,7 @@ int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/artecgroup/dbe61/romstage.c

@@ -57,7 +57,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/asi/mb_5blgp/romstage.c

@@ -30,7 +30,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asi/mb_5blmp/romstage.c

@@ -31,7 +31,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/dsbf/romstage.c

@@ -110,7 +110,7 @@ int mainboard_set_fbd_clock(int speed)
 	}
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	if (bist == 0)

src/mainboard/asus/mew-am/romstage.c

@@ -34,7 +34,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/mew-vm/romstage.c

@@ -34,7 +34,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/p2b-d/romstage.c

@@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/p2b-ds/romstage.c

@@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/p2b-f/romstage.c

@@ -43,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/p2b-ls/romstage.c

@@ -42,7 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/p2b/romstage.c

@@ -42,7 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/p3b-f/romstage.c

@@ -74,7 +74,7 @@ static void disable_spd(void)
 	outb(0x67, PM_IO_BASE + 0x37);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/axus/tc320/romstage.c

@@ -31,7 +31,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/azza/pt-6ibd/romstage.c

@@ -43,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/bachmann/ot200/romstage.c

@@ -46,7 +46,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/bcom/winnet100/romstage.c

@@ -31,7 +31,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/bcom/winnetp680/romstage.c

@@ -81,7 +81,7 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 },
 };
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */

src/mainboard/biostar/m6tba/romstage.c

@@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/compaq/deskpro_en_sff_p600/romstage.c

@@ -42,7 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* FIXME: Should be PC97307! */

src/mainboard/digitallogic/adl855pc/romstage.c

@@ -26,7 +26,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/i855/raminit.c"
 #include "northbridge/intel/i855/reset_test.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	if (bist == 0) {

src/mainboard/digitallogic/msm586seg/romstage.c

@@ -154,7 +154,7 @@ static inline void irqinit(void){
 #endif
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
     volatile int i;

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -30,7 +30,7 @@ int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/dmp/vortex86ex/romstage.c

@@ -300,7 +300,7 @@ static void enable_l2_cache(void)
 	pci_write_config8(NB1, 0xe8, reg_nb_f1_e8);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	device_t dev;

src/mainboard/eaglelion/5bcm/romstage.c

@@ -12,7 +12,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/ecs/p6iwp-fe/romstage.c

@@ -37,7 +37,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);

src/mainboard/emulation/qemu-i440fx/romstage.c

@@ -33,7 +33,7 @@
 
 #include "memory.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int cbmem_was_initted;

src/mainboard/emulation/qemu-q35/romstage.c

@@ -34,7 +34,7 @@
 
 #include "../qemu-i440fx/memory.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int cbmem_was_initted;

src/mainboard/getac/p470/romstage.c

@@ -265,7 +265,7 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;

src/mainboard/gigabyte/ga-6bxc/romstage.c

@@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/gigabyte/ga-6bxe/romstage.c

@@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	it8671f_48mhz_clkin();

src/mainboard/google/butterfly/romstage.c

@@ -112,7 +112,7 @@ static void rcba_config(void)
 	RCBA32(FD) = reg32;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/google/link/romstage.c

@@ -150,7 +150,7 @@ static void copy_spd(struct pei_data *peid)
 	       sizeof(peid->spd_data[0]));
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/google/parrot/romstage.c

@@ -113,7 +113,7 @@ static void rcba_config(void)
 	RCBA32(FD) = reg32;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/google/stout/romstage.c

@@ -154,7 +154,7 @@ static void early_ec_init(void)
 	}
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/hp/e_vectra_p2706t/romstage.c

@@ -37,7 +37,7 @@
 /* TODO: It's a PC87364 actually! */
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* TODO: It's a PC87364 actually! */

src/mainboard/ibase/mb899/romstage.c

@@ -223,7 +223,7 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;

src/mainboard/iei/juki-511p/romstage.c

@@ -32,7 +32,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/iei/nova4899r/romstage.c

@@ -32,7 +32,7 @@
 
 #include "northbridge/amd/gx1/raminit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/iei/pcisa-lx-800-r10/romstage.c

@@ -49,7 +49,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/iei/pm-lx-800-r11/romstage.c

@@ -53,7 +53,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include <cpu/amd/geode_lx/syspreinit.c>
 #include <cpu/amd/geode_lx/msrinit.c>
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/iei/pm-lx2-800-r10/romstage.c

@@ -53,7 +53,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include <cpu/amd/geode_lx/syspreinit.c>
 #include <cpu/amd/geode_lx/msrinit.c>
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/intel/d810e2cb/romstage.c

@@ -35,7 +35,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Set southbridge and Super I/O GPIOs. */

src/mainboard/intel/d945gclf/romstage.c

@@ -156,7 +156,7 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;

src/mainboard/intel/eagleheights/romstage.c

@@ -120,7 +120,7 @@ static void early_config(void)
 	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* int boot_mode = 0; */

src/mainboard/intel/emeraldlake2/romstage.c

@@ -162,7 +162,7 @@ static void setup_sio_gpios(void)
 	outb(0xaa, port);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/intel/jarrell/romstage.c

@@ -38,7 +38,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "debug.c"
 #include "arch/x86/lib/stages.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	static const struct mem_controller mch[] = {

src/mainboard/intel/mtarvon/romstage.c

@@ -51,7 +51,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "arch/x86/lib/stages.c"
 #endif
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	msr_t msr;

src/mainboard/intel/truxton/romstage.c

@@ -51,7 +51,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 
 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	msr_t msr;

src/mainboard/intel/xe7501devkit/romstage.c

@@ -33,7 +33,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 
 // This function MUST appear last (ROMCC limitation)
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/iwave/iWRainbowG6/romstage.c

@@ -332,7 +332,7 @@ static void poulsbo_setup_Stage2Regs(void)
 	printk(BIOS_DEBUG, " done.\n");
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/jetway/j7f2/romstage.c

@@ -86,7 +86,7 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 },
 };
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */

src/mainboard/kontron/986lcd-m/romstage.c

@@ -329,7 +329,7 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;

src/mainboard/kontron/ktqm77/romstage.c

@@ -159,7 +159,7 @@ static void superio_gpio_config(void)
 	pnp_exit_ext_func_mode(dev);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/lanner/em8510/romstage.c

@@ -48,7 +48,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/i855/raminit.c"
 #include "northbridge/intel/i855/reset_test.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	if (bist == 0) {

src/mainboard/lenovo/t520/romstage.c

@@ -108,7 +108,7 @@ static void rcba_config(void)
 	RCBA32(BUC) = 0;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/lenovo/t530/romstage.c

@@ -109,7 +109,7 @@ static void rcba_config(void)
 	RCBA32(BUC) = 0;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/lenovo/t60/romstage.c

@@ -206,7 +206,7 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;

src/mainboard/lenovo/x201/romstage.c

@@ -215,7 +215,7 @@ static void set_fsb_frequency(void)
 	smbus_block_write(0x69, 0, 5, block);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;

src/mainboard/lenovo/x230/romstage.c

@@ -148,7 +148,7 @@ init_usb (void)
 	outw (0x0000, DEFAULT_PMBASE | 0x003c);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int s3resume = 0;

src/mainboard/lenovo/x60/romstage.c

@@ -213,7 +213,7 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;

src/mainboard/lippert/frontrunner/romstage.c

@@ -71,7 +71,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_gx2/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {

src/mainboard/lippert/hurricane-lx/romstage.c

@@ -110,7 +110,7 @@ static void mb_gpio_init(void)
 	}
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/lippert/literunner-lx/romstage.c

@@ -152,7 +152,7 @@ static void mb_gpio_init(void)
 	}
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int err;

src/mainboard/lippert/roadrunner-lx/romstage.c

@@ -85,7 +85,7 @@ static void mb_gpio_init(void)
 	}
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -149,7 +149,7 @@ static void mb_gpio_init(void)
 	}
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int err;

src/mainboard/mitac/6513wu/romstage.c

@@ -35,7 +35,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/msi/ms6119/romstage.c

@@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/msi/ms6147/romstage.c

@@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/msi/ms6156/romstage.c

@@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/msi/ms6178/romstage.c

@@ -36,7 +36,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define DUMMY_DEV PNP_DEV(0x2e, 0)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	w83627hf_set_clksel_48(DUMMY_DEV);

src/mainboard/nec/powermate2000/romstage.c

@@ -34,7 +34,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/nokia/ip530/romstage.c

@@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/packardbell/ms2290/romstage.c

@@ -198,7 +198,7 @@ static inline u16 read_acpi16(u32 addr)
 	return inw(DEFAULT_PMBASE | addr);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;

src/mainboard/pcengines/alix1c/romstage.c

@@ -107,7 +107,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/pcengines/alix2d/romstage.c

@@ -130,7 +130,7 @@ static void mb_gpio_init(void)
 	outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE);       /* Led 3 disabled */
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/rca/rm4100/romstage.c

@@ -94,7 +94,7 @@ static void mb_early_setup(void)
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	if (bist == 0) {

src/mainboard/roda/rk886ex/romstage.c

@@ -251,7 +251,7 @@ static void init_artec_dongle(void)
 	outb(0xf4, 0x88);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;

src/mainboard/roda/rk9/romstage.c

@@ -120,7 +120,7 @@ static void default_superio_gpio_setup(void)
 	outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	sysinfo_t sysinfo;

src/mainboard/samsung/lumpy/romstage.c

@@ -132,7 +132,7 @@ static void early_pch_init(void)
 	pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/samsung/stumpy/romstage.c

@@ -172,7 +172,7 @@ static void setup_sio_gpios(void)
 	it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;

src/mainboard/soyo/sy-6ba-plus-iii/romstage.c

@@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/supermicro/x6dai_g/romstage.c

@@ -42,7 +42,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "arch/x86/lib/stages.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	static const struct mem_controller mch[] = {

src/mainboard/supermicro/x6dhe_g/romstage.c

@@ -46,7 +46,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "arch/x86/lib/stages.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	static const struct mem_controller mch[] = {

src/mainboard/supermicro/x6dhe_g2/romstage.c

@@ -43,7 +43,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "arch/x86/lib/stages.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	static const struct mem_controller mch[] = {

src/mainboard/supermicro/x6dhr_ig/romstage.c

@@ -45,7 +45,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "arch/x86/lib/stages.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	static const struct mem_controller mch[] = {

src/mainboard/supermicro/x6dhr_ig2/romstage.c

@@ -45,7 +45,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "arch/x86/lib/stages.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	static const struct mem_controller mch[] = {

src/mainboard/supermicro/x7db8/romstage.c

@@ -111,7 +111,7 @@ int mainboard_set_fbd_clock(int speed)
 	}
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	if (bist == 0)

src/mainboard/technologic/ts5300/romstage.c

@@ -136,7 +136,7 @@ static void hard_reset(void)
 	while (1) ;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	volatile int i;

src/mainboard/televideo/tc7020/romstage.c

@@ -31,7 +31,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);