Artec Group dbe61 mainboard support.
Now uses CAR. New code for SPD-less memory implementation. Updated IRQ routing. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
parent
dfb3c130d5
commit
a0aaa752dd
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@ -47,27 +47,17 @@ driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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if USE_DCACHE_RAM
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#compile cache_as_ram.c to auto.inc
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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@ -104,7 +94,7 @@ ldscript /arch/i386/lib/id.lds
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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# mainboardinit ./failover.inc
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end
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###
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@ -115,7 +105,11 @@ end
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit ./auto.inc
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if USE_DCACHE_RAM
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mainboardinit cpu/amd/model_lx/cache_as_ram.inc
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mainboardinit ./cache_as_ram_auto.inc
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end
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##
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## Include the secondary Configuration files
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@ -124,70 +118,44 @@ dir /pc80
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config chip.h
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chip northbridge/amd/lx
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register "irqmap" = "0xcba5"
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device pci_domain 0 on
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Graphics
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chip southbridge/amd/cs5536
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# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
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# SIRQ Mode = Active(Quiet) mode. Save power....
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# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
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register "lpc_serirq_enable" = "0x00001002"
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register "lpc_serirq_polarity" = "0x0000EFFD"
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register "lpc_serirq_mode" = "1"
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" #0: host, 1:device
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register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
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register "com1_enable" = "0"
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register "com1_address" = "0x2F8"
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register "com1_irq" = "3"
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register "com2_enable" = "1"
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register "com2_address" = "0x3F8"
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register "com2_irq" = "4"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci b.0 on end # Slot 3
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device pci c.0 on end # Slot 4
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device pci d.0 on end # Slot 1
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device pci e.0 on end # Slot 2
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device apic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 1.0 on end # Host Bridge
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# chip drivers/pci/realmode
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# device pci 1.1 on end # VGA
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# register "rom_address" = "0xfffc0000" # at the beginning of 256k
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# end
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device pci 1.2 off end # AES
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chip southbridge/amd/cs5536_lx
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register "enable_ide_nand_flash" = "0"
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register "isa_irq" = "0"
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#register "flash_irq" = "14"
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## IDE IRQ
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register "enable_ide_irq" = "0"
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register "audio_irq" = "5"
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register "usb_irq" = "7"
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register "uart0_irq" = "0"
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register "uart1_irq" = "4"
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## PCI INTA ... INTD and their GPIO pins
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## int==0: disable
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register "pci_int[0]" = "0"
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register "pci_int[1]" = "10"
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register "pci_int[2]" = "0"
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register "pci_int[3]" = "0"
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register "pci_int_pin[0]" = "0"
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register "pci_int_pin[1]" = "7"
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register "pci_int_pin[2]" = "0"
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register "pci_int_pin[3]" = "0"
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# Keyboard Emulation Logic IRQs
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# Enable keyboard IRQ2
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register "enable_kel_keyb_irq" = "0"
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# Enable mouse IRQ12
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register "enable_kel_mouse_irq" = "0"
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# Configure KEL Emulation IRQ, 0 to disable
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register "kel_emul_irq" = "0"
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device pci f.0 on end # ISA Bridge
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device pci f.1 on end # Flash controller
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device pci f.2 off end # IDE controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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device pci f.6 off end # UDC controller
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device pci f.7 off end # OTG controller
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end
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# chip drivers/pci/rtl8139
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## device pci d.0 on end # Realtek LAN
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# register "nic_irq" = "10"
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# end
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end
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end
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@ -23,6 +23,7 @@ uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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@ -44,6 +45,9 @@ uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_VIDEO_MB
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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@ -51,8 +55,8 @@ default ROM_SIZE = 256*1024
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###
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### Build options
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###
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default CONFIG_CONSOLE_VGA=1
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default CONFIG_PCI_ROM_RUN=1
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default CONFIG_CONSOLE_VGA=0
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default CONFIG_PCI_ROM_RUN=0
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default CONFIG_VIDEO_MB=8
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##
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@ -78,8 +82,8 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=0
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default IRQ_SLOT_COUNT=6
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=3
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#object irq_tables.o
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@ -96,6 +100,13 @@ default HAVE_OPTION_TABLE=0
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM=1
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default DCACHE_RAM_BASE=0xc8000
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default DCACHE_RAM_SIZE=0x08000
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##
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## Use a small 8K stack
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##
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@ -1,134 +0,0 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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//#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/lxdef.h>
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//#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/lx/raminit.h"
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static inline unsigned int fls(unsigned int x)
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{
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int r;
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__asm__("bsfl %1,%0\n\t"
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"jnz 1f\n\t"
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"movl $32,%0\n"
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"1:" : "=r" (r) : "g" (x));
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return r;
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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* component Banks (byte 17) * module banks, side (byte 5) *
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* width in bits (byte 6,7)
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* = Density per side (byte 31) * number of sides (byte 5) */
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/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
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msr_t msr;
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unsigned char module_banks, val;
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msr.hi = 0x10075012;
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msr.lo = 0x00000040;
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wrmsr(MC_CF07_DATA, msr); //GX3
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/* timing and mode ... */
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//msr = rdmsr(0x20000019);
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/* per standard bios settings */
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/*
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msr.hi = 0x18000108;
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msr.lo =
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(6<<28) | // cas_lat
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(10<<24)| // ref2act
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(7<<20)| // act2pre
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(3<<16)| // pre2act
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(3<<12)| // act2cmd
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(2<<8)| // act2act
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(2<<6)| // dplwr
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(2<<4)| // dplrd
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(3); // dal
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* the msr value reported by quanta is very, very different.
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* we will go with that value for now.
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*
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//msr.lo = 0x286332a3;
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*/
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//wrmsr(0x20000019, msr); //GX3
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}
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#include "northbridge/amd/lx/raminit.c"
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#include "sdram/generic_sdram.c"
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/* CPU and GLIU mult/div */
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#define PLLMSRhi 0x0000039C
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/* Hold Count - how long we will sit in reset */
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#define PLLMSRlo 0x00DE0000
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#include "northbridge/amd/lx/pll_reset.c"
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#include "cpu/amd/model_lx/cpureginit.c"
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#include "cpu/amd/model_lx/syspreinit.c"
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static void msr_init(void)
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{
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__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
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}
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl [] = {
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{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
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};
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SystemPreInit(); //GX3 OK
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msr_init(); //GX3 OK
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cs5536_early_setup(); //GX3 OK
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/* NOTE: must do this AFTER the early_setup!
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* it is counting on some early MSR setup
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* for cs5536
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*/
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cs5536_setup_onchipuart(); //GX3 OK
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uart_init(); //GX3 OK
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console_init(); //GX3 OK
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pll_reset(); //GX3 OK
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cpuRegInit(); //GX3 OK
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print_err("done cpuRegInit\n");
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sdram_initialize(1, memctrl); //GX3 OK almost
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/* Check all of memory */
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//ram_check(0x00000000, 640*1024);
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}
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@ -0,0 +1,215 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/lxdef.h>
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#include <cpu/amd/geode_post_code.h>
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#include "southbridge/amd/cs5536/cs5536.h"
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#include "spd_table.h"
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#define POST_CODE(x) outb(x, 0x80)
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#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
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#include "southbridge/amd/cs5536/cs5536_early_setup.c"
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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static int spd_read_byte(unsigned device, unsigned address)
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{
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int i;
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if (device == DIMM0){
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for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){
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if (spd_table[i].address == address){
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return spd_table[i].data;
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}
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}
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}
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/* returns 0xFF on any failures */
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return 0xFF;
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}
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#define ManualConf 0 /* Do automatic strapped PLL config */
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/* CPU and GLIU mult/div 500/266*/
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#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */
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/* Hold Count - how long we will sit in reset */
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#define PLLMSRlo 0x00DE6000
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#include "northbridge/amd/lx/raminit.h"
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#include "northbridge/amd/lx/pll_reset.c"
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#include "northbridge/amd/lx/raminit.c"
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#include "sdram/generic_sdram.c"
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#include "cpu/amd/model_lx/cpureginit.c"
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#include "cpu/amd/model_lx/syspreinit.c"
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static void msr_init(void)
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{
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msr_t msr;
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/* Setup access to the cache for under 1MB. */
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msr.hi = 0x24fffc02;
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msr.lo = 0x1000A000; /* 0-A0000 write back */
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wrmsr(CPU_RCONF_DEFAULT, msr);
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msr.hi = 0x0; /* write back */
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msr.lo = 0x0;
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wrmsr(CPU_RCONF_A0_BF, msr);
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wrmsr(CPU_RCONF_C0_DF, msr);
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wrmsr(CPU_RCONF_E0_FF, msr);
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||||
|
||||
/* Setup access to the cache for under 640K. Note MC not setup yet. */
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU0 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU0 + 0x21, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0xfff80;
|
||||
wrmsr(MSR_GLIU1 + 0x20, msr);
|
||||
|
||||
msr.hi = 0x20000000;
|
||||
msr.lo = 0x80fffe0;
|
||||
wrmsr(MSR_GLIU1 + 0x21, msr);
|
||||
|
||||
}
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Early mainboard specific GPIO setup */
|
||||
}
|
||||
|
||||
static void cs5536_setup_onchipuart2(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
/* GPIO4 - UART2_TX */
|
||||
/* Set: Output Enable (0x4) */
|
||||
outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
|
||||
/* Set: OUTAUX1 Select (0x10) */
|
||||
outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
|
||||
/* GPIO4 - UART2_RX */
|
||||
/* Set: Input Enable (0x20) */
|
||||
outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
|
||||
/* Set: INAUX1 Select (0x34) */
|
||||
outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
|
||||
|
||||
/* Set: GPIO 3 + 3 Pull Up (0x18) */
|
||||
outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
|
||||
|
||||
/* set address to 3F8 */
|
||||
msr = rdmsr(MDD_LEG_IO);
|
||||
msr.lo |= 0x7 << 20;
|
||||
wrmsr(MDD_LEG_IO, msr);
|
||||
|
||||
/* Bit 1 = DEVEN (device enable)
|
||||
* Bit 4 = EN_BANKS (allow access to the upper banks
|
||||
*/
|
||||
msr.lo = (1 << 4) | (1 << 1);
|
||||
msr.hi = 0;
|
||||
|
||||
/* enable COM2 */
|
||||
wrmsr(MDD_UART2_CONF, msr);
|
||||
}
|
||||
|
||||
void cache_as_ram_main(void)
|
||||
{
|
||||
POST_CODE(0x01);
|
||||
|
||||
static const struct mem_controller memctrl[] = {
|
||||
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
|
||||
};
|
||||
|
||||
SystemPreInit();
|
||||
msr_init();
|
||||
|
||||
cs5536_early_setup();
|
||||
|
||||
/* NOTE: must do this AFTER the early_setup!
|
||||
* it is counting on some early MSR setup
|
||||
* for cs5536
|
||||
*/
|
||||
/* cs5536_disable_internal_uart disable them. Set them up now... */
|
||||
cs5536_setup_onchipuart2(); /* dbe61 uses UART2 as COM1 */
|
||||
mb_gpio_init();
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
pll_reset(ManualConf);
|
||||
|
||||
cpuRegInit();
|
||||
|
||||
sdram_initialize(1, memctrl);
|
||||
|
||||
/* Dump memory configuratation */
|
||||
/*{
|
||||
msr_t msr;
|
||||
msr = rdmsr(MC_CF07_DATA);
|
||||
print_debug("MC_CF07_DATA: ");
|
||||
print_debug_hex32(MC_CF07_DATA);
|
||||
print_debug(" value is: ");
|
||||
print_debug_hex32(msr.hi);
|
||||
print_debug(":");
|
||||
print_debug_hex32(msr.lo);
|
||||
print_debug(" \n");
|
||||
|
||||
msr = rdmsr(MC_CF1017_DATA);
|
||||
print_debug("MC_CF1017_DATA: ");
|
||||
print_debug_hex32(MC_CF1017_DATA);
|
||||
print_debug(" value is: ");
|
||||
print_debug_hex32(msr.hi);
|
||||
print_debug(":");
|
||||
print_debug_hex32(msr.lo);
|
||||
print_debug(" \n");
|
||||
|
||||
msr = rdmsr(MC_CF8F_DATA);
|
||||
print_debug("MC_CF8F_DATA: ");
|
||||
print_debug_hex32(MC_CF8F_DATA);
|
||||
print_debug(" value is: ");
|
||||
print_debug_hex32(msr.hi);
|
||||
print_debug(":");
|
||||
print_debug_hex32(msr.lo);
|
||||
msr = rdmsr(MC_CF8F_DATA);
|
||||
print_debug(" \n");
|
||||
}*/
|
||||
|
||||
/* Check memory. */
|
||||
/* ram_check(0x00000000, 640 * 1024); */
|
||||
|
||||
/* Memory is setup. Return to cache_as_ram.inc and continue to boot */
|
||||
return;
|
||||
}
|
||||
|
|
@ -1,60 +1,105 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
|
||||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
#include "../../../southbridge/amd/cs5536/cs5536.h"
|
||||
|
||||
#define ID_SLOT_PCI_NET 1 // ThinCan ethernet
|
||||
#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1
|
||||
#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2
|
||||
#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3
|
||||
#define ID_EMBED_PCI 0xff // onboard PCI device
|
||||
/* Platform IRQs */
|
||||
#define PIRQA 10
|
||||
#define PIRQB 11
|
||||
#define PIRQC 10
|
||||
#define PIRQD 11
|
||||
|
||||
// CS5535 PCI INT[A-D] Interrupt Routing lines.
|
||||
#define NO_CONNECT 0 // not used
|
||||
#define CS_PCI_INTA 1 // PCI INTA
|
||||
#define CS_PCI_INTB 2 // PCI INTB
|
||||
#define CS_PCI_INTC 3 // PCI INTC
|
||||
#define CS_PCI_INTD 4 // PCI INTD
|
||||
/* Map */
|
||||
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
|
||||
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
|
||||
|
||||
// IRQ bitmap reference line FEDCBA9876543210
|
||||
// 0000110000100000b
|
||||
#define PCI_IRQ 0xc20 // PCI allowed IRQs here
|
||||
/* Link */
|
||||
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
|
||||
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
|
||||
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
|
||||
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table =
|
||||
{
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*6, /* there can be total 2 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0x0800, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1022, /* Vendor */
|
||||
0x208f, /* Device */
|
||||
0x00000000, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
|
||||
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x100B, /* Vendor */
|
||||
0x002B, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
|
||||
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
// Geode GX3 Host Bridge and VGA Graphics
|
||||
{0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
|
||||
// Realtek RTL8100/8139 Network Controller
|
||||
{0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0},
|
||||
// Reserved for future extensions
|
||||
{0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
|
||||
// Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
|
||||
{0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
|
||||
// Reserved for future extensions
|
||||
{0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
|
||||
// Reserved for future extensions
|
||||
{0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
|
||||
}
|
||||
/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
|
||||
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
|
||||
{0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
int i, j, k, num_entries;
|
||||
unsigned char pirq[4];
|
||||
uint16_t chipset_irq_map;
|
||||
uint32_t pciAddr, pirtable_end;
|
||||
struct irq_routing_table *pirq_tbl;
|
||||
|
||||
pirtable_end = copy_pirq_routing_table(addr);
|
||||
|
||||
/* Set up chipset IRQ steering. */
|
||||
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
|
||||
chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
|
||||
printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
|
||||
chipset_irq_map);
|
||||
outl(pciAddr & ~3, 0xCF8);
|
||||
outl(chipset_irq_map, 0xCFC);
|
||||
|
||||
pirq_tbl = (struct irq_routing_table *)(addr);
|
||||
num_entries = (pirq_tbl->size - 32) / 16;
|
||||
|
||||
/* Set PCI IRQs. */
|
||||
for (i = 0; i < num_entries; i++) {
|
||||
printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
|
||||
pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
|
||||
for (j = 0; j < 4; j++) {
|
||||
printk_debug("INT: %c bitmap: %x ", 'A' + j,
|
||||
pirq_tbl->slots[i].irq[j].bitmap);
|
||||
for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
|
||||
pirq[j] = k;
|
||||
printk_debug("PIRQ: %d\n", k);
|
||||
}
|
||||
|
||||
/* Bus, device, slots IRQs for {A,B,C,D}. */
|
||||
pci_assign_irqs(pirq_tbl->slots[i].bus,
|
||||
pirq_tbl->slots[i].devfn >> 3, pirq);
|
||||
}
|
||||
|
||||
/* Put the PIR table in memory and checksum. */
|
||||
return pirtable_end;
|
||||
}
|
||||
|
|
@ -1,3 +1,22 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
|
|
@ -6,20 +25,15 @@
|
|||
#include <arch/io.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/lxdef.h>
|
||||
#include "../../../southbridge/amd/cs5536/cs5536.h"
|
||||
#include "chip.h"
|
||||
|
||||
#define DIVIL_LBAR_GPIO 0x5140000c
|
||||
|
||||
static void init_gpio()
|
||||
{
|
||||
msr_t msr;
|
||||
printk_debug("Initializing GPIO module...\n");
|
||||
printk_debug("Checking GPIO module...\n");
|
||||
|
||||
// initialize the GPIO LBAR
|
||||
msr.lo = GPIO_BASE;
|
||||
msr.hi = 0x0000f001;
|
||||
wrmsr(DIVIL_LBAR_GPIO, msr);
|
||||
msr = rdmsr(DIVIL_LBAR_GPIO);
|
||||
msr = rdmsr(MDD_LBAR_GPIO);
|
||||
printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* This file is part of the LinuxBIOS project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <spd.h>
|
||||
|
||||
struct spd_entry {
|
||||
unsigned int address;
|
||||
unsigned int data;
|
||||
};
|
||||
|
||||
/* Save space by using a short list of SPD values used by Geode LX Memory init */
|
||||
/* 128MB */
|
||||
const struct spd_entry spd_table [] =
|
||||
{
|
||||
{SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */
|
||||
{SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */
|
||||
{SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */
|
||||
{SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */
|
||||
{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x50}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
|
||||
{SPD_REFRESH, 0x82}, /* Refresh rate/type */
|
||||
{SPD_PRIMARY_SDRAM_WIDTH, 0x08}, /* SDRAM width (primary SDRAM) */
|
||||
{SPD_NUM_BANKS_PER_SDRAM, 0x04}, /* SDRAM device attributes, number of banks on SDRAM device */
|
||||
{SPD_ACCEPTABLE_CAS_LATENCIES, 0x1C}, /* SDRAM device attributes, CAS latency */
|
||||
{SPD_MODULE_ATTRIBUTES, 0x20}, /* SDRAM module attributes */
|
||||
{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xC0}, /* SDRAM device attributes, general */
|
||||
{SPD_SDRAM_CYCLE_TIME_2ND, 0x60}, /* SDRAM cycle time (2nd highest CAS latency) */
|
||||
{SPD_SDRAM_CYCLE_TIME_3RD, 0x75}, /* SDRAM cycle time (3rd highest CAS latency) */
|
||||
{SPD_MIN_ROW_PRECHARGE_TIME, 0x3C}, /* Minimum row precharge time (Trp) */
|
||||
{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x28}, /* Minimum row active to row active (Trrd) */
|
||||
{SPD_MIN_RAS_TO_CAS_DELAY, 0x3C}, /* Minimum RAS to CAS delay (Trcd) */
|
||||
{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x28}, /* Minimum RAS pulse width (Tras) */
|
||||
{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */
|
||||
{SPD_CMD_SIGNAL_INPUT_HOLD_TIME, 0x60}, /* Command and address signal input hold time */
|
||||
{SPD_tRC, 0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
|
||||
{SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
|
||||
};
|
||||
|
|
@ -3,14 +3,21 @@
|
|||
target dbe61
|
||||
mainboard artecgroup/dbe61
|
||||
|
||||
# HACK to get the right TSC support.
|
||||
option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
|
||||
option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
|
||||
|
||||
## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
|
||||
## (normal AND fallback images and payloads).
|
||||
## leave 64k for vsa and 32K for video ROM
|
||||
option ROM_SIZE = 1024*256 - 64*1024 - 32 * 1024
|
||||
## leave 36k for vsa and 32K for video ROM
|
||||
#option ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024
|
||||
|
||||
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
|
||||
#No VGA for now
|
||||
option ROM_SIZE = 1024*512 - 36*1024
|
||||
|
||||
# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
|
||||
## not including any payload.
|
||||
option ROM_IMAGE_SIZE=64*1024
|
||||
|
||||
|
|
@ -21,7 +28,7 @@ option MAXIMUM_CONSOLE_LOGLEVEL = 11
|
|||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
||||
payload /tmp/filo.elf
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
buildrom ./linuxbios.rom ROM_SIZE "fallback"
|
||||
buildrom ./dbe61.rom ROM_SIZE "fallback"
|
||||
|
|
|
|||
Loading…
Reference in New Issue