Artec Group dbe61 mainboard support.

Now uses CAR.
New code for SPD-less memory implementation.
Updated IRQ routing.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones 2007-06-20 23:45:44 +00:00
parent dfb3c130d5
commit a0aaa752dd
8 changed files with 458 additions and 279 deletions

View File

@ -47,27 +47,17 @@ driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o #object reset.o
##
## Romcc output if USE_DCACHE_RAM
## #compile cache_as_ram.c to auto.inc
makerule ./failover.E makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/failover.c ./romcc" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
## ##
## Build our 16 bit and 32 bit linuxBIOS entry code ## Build our 16 bit and 32 bit linuxBIOS entry code
@ -104,7 +94,7 @@ ldscript /arch/i386/lib/id.lds
### ###
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc # mainboardinit ./failover.inc
end end
### ###
@ -115,7 +105,11 @@ end
## Setup RAM ## Setup RAM
## ##
mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit ./auto.inc
if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
end
## ##
## Include the secondary Configuration files ## Include the secondary Configuration files
@ -124,70 +118,44 @@ dir /pc80
config chip.h config chip.h
chip northbridge/amd/lx chip northbridge/amd/lx
register "irqmap" = "0xcba5" device pci_domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
chip southbridge/amd/cs5536
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
register "lpc_serirq_enable" = "0x00001002"
register "lpc_serirq_polarity" = "0x0000EFFD"
register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" #0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "0"
register "com1_address" = "0x2F8"
register "com1_irq" = "3"
register "com2_enable" = "1"
register "com2_address" = "0x3F8"
register "com2_irq" = "4"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci b.0 on end # Slot 3
device pci c.0 on end # Slot 4
device pci d.0 on end # Slot 1
device pci e.0 on end # Slot 2
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device apic_cluster 0 on device apic_cluster 0 on
chip cpu/amd/model_lx chip cpu/amd/model_lx
device apic 0 on end device apic 0 on end
end end
end end
device pci_domain 0 on
device pci 1.0 on end # Host Bridge
# chip drivers/pci/realmode
# device pci 1.1 on end # VGA
# register "rom_address" = "0xfffc0000" # at the beginning of 256k
# end
device pci 1.2 off end # AES
chip southbridge/amd/cs5536_lx
register "enable_ide_nand_flash" = "0"
register "isa_irq" = "0"
#register "flash_irq" = "14"
## IDE IRQ
register "enable_ide_irq" = "0"
register "audio_irq" = "5"
register "usb_irq" = "7"
register "uart0_irq" = "0"
register "uart1_irq" = "4"
## PCI INTA ... INTD and their GPIO pins
## int==0: disable
register "pci_int[0]" = "0"
register "pci_int[1]" = "10"
register "pci_int[2]" = "0"
register "pci_int[3]" = "0"
register "pci_int_pin[0]" = "0"
register "pci_int_pin[1]" = "7"
register "pci_int_pin[2]" = "0"
register "pci_int_pin[3]" = "0"
# Keyboard Emulation Logic IRQs
# Enable keyboard IRQ2
register "enable_kel_keyb_irq" = "0"
# Enable mouse IRQ12
register "enable_kel_mouse_irq" = "0"
# Configure KEL Emulation IRQ, 0 to disable
register "kel_emul_irq" = "0"
device pci f.0 on end # ISA Bridge
device pci f.1 on end # Flash controller
device pci f.2 off end # IDE controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
device pci f.6 off end # UDC controller
device pci f.7 off end # OTG controller
end
# chip drivers/pci/rtl8139
## device pci d.0 on end # Realtek LAN
# register "nic_irq" = "10"
# end
end
end end

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@ -23,6 +23,7 @@ uses ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE uses PAYLOAD_SIZE
uses _ROMBASE uses _ROMBASE
uses _RAMBASE uses _RAMBASE
@ -44,6 +45,9 @@ uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_VGA uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
## ROM_SIZE is the size of boot ROM that this board will use. ## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024 default ROM_SIZE = 256*1024
@ -51,8 +55,8 @@ default ROM_SIZE = 256*1024
### ###
### Build options ### Build options
### ###
default CONFIG_CONSOLE_VGA=1 default CONFIG_CONSOLE_VGA=0
default CONFIG_PCI_ROM_RUN=1 default CONFIG_PCI_ROM_RUN=0
default CONFIG_VIDEO_MB=8 default CONFIG_VIDEO_MB=8
## ##
@ -78,8 +82,8 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## ##
## Build code to export a programmable irq routing table ## Build code to export a programmable irq routing table
## ##
default HAVE_PIRQ_TABLE=0 default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=6 default IRQ_SLOT_COUNT=3
#object irq_tables.o #object irq_tables.o
@ -96,6 +100,13 @@ default HAVE_OPTION_TABLE=0
default ROM_IMAGE_SIZE = 65536 default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072 default FALLBACK_SIZE = 131072
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xc8000
default DCACHE_RAM_SIZE=0x08000
## ##
## Use a small 8K stack ## Use a small 8K stack
## ##

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@ -1,134 +0,0 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
//#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
//#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/lx/raminit.h"
static inline unsigned int fls(unsigned int x)
{
int r;
__asm__("bsfl %1,%0\n\t"
"jnz 1f\n\t"
"movl $32,%0\n"
"1:" : "=r" (r) : "g" (x));
return r;
}
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
* component Banks (byte 17) * module banks, side (byte 5) *
* width in bits (byte 6,7)
* = Density per side (byte 31) * number of sides (byte 5) */
/* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
msr_t msr;
unsigned char module_banks, val;
msr.hi = 0x10075012;
msr.lo = 0x00000040;
wrmsr(MC_CF07_DATA, msr); //GX3
/* timing and mode ... */
//msr = rdmsr(0x20000019);
/* per standard bios settings */
/*
msr.hi = 0x18000108;
msr.lo =
(6<<28) | // cas_lat
(10<<24)| // ref2act
(7<<20)| // act2pre
(3<<16)| // pre2act
(3<<12)| // act2cmd
(2<<8)| // act2act
(2<<6)| // dplwr
(2<<4)| // dplrd
(3); // dal
* the msr value reported by quanta is very, very different.
* we will go with that value for now.
*
//msr.lo = 0x286332a3;
*/
//wrmsr(0x20000019, msr); //GX3
}
#include "northbridge/amd/lx/raminit.c"
#include "sdram/generic_sdram.c"
/* CPU and GLIU mult/div */
#define PLLMSRhi 0x0000039C
/* Hold Count - how long we will sit in reset */
#define PLLMSRlo 0x00DE0000
#include "northbridge/amd/lx/pll_reset.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
static void msr_init(void)
{
__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
}
static void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
};
SystemPreInit(); //GX3 OK
msr_init(); //GX3 OK
cs5536_early_setup(); //GX3 OK
/* NOTE: must do this AFTER the early_setup!
* it is counting on some early MSR setup
* for cs5536
*/
cs5536_setup_onchipuart(); //GX3 OK
uart_init(); //GX3 OK
console_init(); //GX3 OK
pll_reset(); //GX3 OK
cpuRegInit(); //GX3 OK
print_err("done cpuRegInit\n");
sdram_initialize(1, memctrl); //GX3 OK almost
/* Check all of memory */
//ram_check(0x00000000, 640*1024);
}

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@ -0,0 +1,215 @@
/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "spd_table.h"
#define POST_CODE(x) outb(x, 0x80)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#define DIMM0 0xA0
#define DIMM1 0xA2
static int spd_read_byte(unsigned device, unsigned address)
{
int i;
if (device == DIMM0){
for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){
if (spd_table[i].address == address){
return spd_table[i].data;
}
}
}
/* returns 0xFF on any failures */
return 0xFF;
}
#define ManualConf 0 /* Do automatic strapped PLL config */
/* CPU and GLIU mult/div 500/266*/
#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */
/* Hold Count - how long we will sit in reset */
#define PLLMSRlo 0x00DE6000
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
#include "sdram/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
static void msr_init(void)
{
msr_t msr;
/* Setup access to the cache for under 1MB. */
msr.hi = 0x24fffc02;
msr.lo = 0x1000A000; /* 0-A0000 write back */
wrmsr(CPU_RCONF_DEFAULT, msr);
msr.hi = 0x0; /* write back */
msr.lo = 0x0;
wrmsr(CPU_RCONF_A0_BF, msr);
wrmsr(CPU_RCONF_C0_DF, msr);
wrmsr(CPU_RCONF_E0_FF, msr);
/* Setup access to the cache for under 640K. Note MC not setup yet. */
msr.hi = 0x20000000;
msr.lo = 0xfff80;
wrmsr(MSR_GLIU0 + 0x20, msr);
msr.hi = 0x20000000;
msr.lo = 0x80fffe0;
wrmsr(MSR_GLIU0 + 0x21, msr);
msr.hi = 0x20000000;
msr.lo = 0xfff80;
wrmsr(MSR_GLIU1 + 0x20, msr);
msr.hi = 0x20000000;
msr.lo = 0x80fffe0;
wrmsr(MSR_GLIU1 + 0x21, msr);
}
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup */
}
static void cs5536_setup_onchipuart2(void)
{
msr_t msr;
/* GPIO4 - UART2_TX */
/* Set: Output Enable (0x4) */
outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
/* Set: OUTAUX1 Select (0x10) */
outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
/* GPIO4 - UART2_RX */
/* Set: Input Enable (0x20) */
outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
/* Set: INAUX1 Select (0x34) */
outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
/* Set: GPIO 3 + 3 Pull Up (0x18) */
outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
/* set address to 3F8 */
msr = rdmsr(MDD_LEG_IO);
msr.lo |= 0x7 << 20;
wrmsr(MDD_LEG_IO, msr);
/* Bit 1 = DEVEN (device enable)
* Bit 4 = EN_BANKS (allow access to the upper banks
*/
msr.lo = (1 << 4) | (1 << 1);
msr.hi = 0;
/* enable COM2 */
wrmsr(MDD_UART2_CONF, msr);
}
void cache_as_ram_main(void)
{
POST_CODE(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* NOTE: must do this AFTER the early_setup!
* it is counting on some early MSR setup
* for cs5536
*/
/* cs5536_disable_internal_uart disable them. Set them up now... */
cs5536_setup_onchipuart2(); /* dbe61 uses UART2 as COM1 */
mb_gpio_init();
uart_init();
console_init();
pll_reset(ManualConf);
cpuRegInit();
sdram_initialize(1, memctrl);
/* Dump memory configuratation */
/*{
msr_t msr;
msr = rdmsr(MC_CF07_DATA);
print_debug("MC_CF07_DATA: ");
print_debug_hex32(MC_CF07_DATA);
print_debug(" value is: ");
print_debug_hex32(msr.hi);
print_debug(":");
print_debug_hex32(msr.lo);
print_debug(" \n");
msr = rdmsr(MC_CF1017_DATA);
print_debug("MC_CF1017_DATA: ");
print_debug_hex32(MC_CF1017_DATA);
print_debug(" value is: ");
print_debug_hex32(msr.hi);
print_debug(":");
print_debug_hex32(msr.lo);
print_debug(" \n");
msr = rdmsr(MC_CF8F_DATA);
print_debug("MC_CF8F_DATA: ");
print_debug_hex32(MC_CF8F_DATA);
print_debug(" value is: ");
print_debug_hex32(msr.hi);
print_debug(":");
print_debug_hex32(msr.lo);
msr = rdmsr(MC_CF8F_DATA);
print_debug(" \n");
}*/
/* Check memory. */
/* ram_check(0x00000000, 640 * 1024); */
/* Memory is setup. Return to cache_as_ram.inc and continue to boot */
return;
}

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@ -1,60 +1,105 @@
/* This file was generated by getpir.c, do not modify! /*
(but if you do, please run checkpir on it to verify) * This file is part of the LinuxBIOS project.
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
* *
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM * Copyright (C) 2007 Advanced Micro Devices, Inc.
*/ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/pirq_routing.h> #include <arch/pirq_routing.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/pirq_routing.h>
#include "../../../southbridge/amd/cs5536/cs5536.h"
#define ID_SLOT_PCI_NET 1 // ThinCan ethernet /* Platform IRQs */
#define ID_SLOT_PCI_RSVD1 2 // reserved entry 1 #define PIRQA 10
#define ID_SLOT_PCI_RSVD3 3 // reserved entry 2 #define PIRQB 11
#define ID_SLOT_PCI_RSVD2 4 // reserved entry 3 #define PIRQC 10
#define ID_EMBED_PCI 0xff // onboard PCI device #define PIRQD 11
// CS5535 PCI INT[A-D] Interrupt Routing lines. /* Map */
#define NO_CONNECT 0 // not used #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define CS_PCI_INTA 1 // PCI INTA #define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define CS_PCI_INTB 2 // PCI INTB #define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define CS_PCI_INTC 3 // PCI INTC #define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
#define CS_PCI_INTD 4 // PCI INTD
// IRQ bitmap reference line FEDCBA9876543210 /* Link */
// 0000110000100000b #define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define PCI_IRQ 0xc20 // PCI allowed IRQs here #define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
const struct irq_routing_table intel_irq_routing_table = const struct irq_routing_table intel_irq_routing_table = {
{ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */
PIRQ_VERSION, /* u16 version */ 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
32+16*6, /* there can be total 2 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */
0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */
0x0800, /* IRQs devoted exclusively to PCI usage */ 0x100B, /* Vendor */
0x1022, /* Vendor */ 0x002B, /* Device */
0x208f, /* Device */ 0, /* Crap (miniport) */
0x00000000, /* Crap (miniport) */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{ {
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
// Geode GX3 Host Bridge and VGA Graphics /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0, 0x01<<3, {{CS_PCI_INTA, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}, {NO_CONNECT, PCI_IRQ}}, ID_EMBED_PCI, 0x0}, {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
// Realtek RTL8100/8139 Network Controller {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0, 0x0d<<3, {{CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}}, ID_SLOT_PCI_NET, 0x0}, {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
// Reserved for future extensions }
{0, 0x0c<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_SLOT_PCI_RSVD1, 0x0},
// Geode CS5535/CS5536 IO Companion: USB controllers, IDE, Audio.
{0, 0x0f<<3, {{CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}}, ID_EMBED_PCI, 0x0},
// Reserved for future extensions
{0, 0x0e<<3, {{CS_PCI_INTC, PCI_IRQ}, {CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}}, ID_SLOT_PCI_RSVD2, 0x0},
// Reserved for future extensions
{0, 0x0b<<3, {{CS_PCI_INTD, PCI_IRQ}, {CS_PCI_INTA, PCI_IRQ}, {CS_PCI_INTB, PCI_IRQ}, {CS_PCI_INTC, PCI_IRQ}}, ID_SLOT_PCI_RSVD3, 0x0}
}
}; };
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {
return copy_pirq_routing_table(addr); int i, j, k, num_entries;
} unsigned char pirq[4];
uint16_t chipset_irq_map;
uint32_t pciAddr, pirtable_end;
struct irq_routing_table *pirq_tbl;
pirtable_end = copy_pirq_routing_table(addr);
/* Set up chipset IRQ steering. */
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);
outl(pciAddr & ~3, 0xCF8);
outl(chipset_irq_map, 0xCFC);
pirq_tbl = (struct irq_routing_table *)(addr);
num_entries = (pirq_tbl->size - 32) / 16;
/* Set PCI IRQs. */
for (i = 0; i < num_entries; i++) {
printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) {
printk_debug("INT: %c bitmap: %x ", 'A' + j,
pirq_tbl->slots[i].irq[j].bitmap);
for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */
pirq[j] = k;
printk_debug("PIRQ: %d\n", k);
}
/* Bus, device, slots IRQs for {A,B,C,D}. */
pci_assign_irqs(pirq_tbl->slots[i].bus,
pirq_tbl->slots[i].devfn >> 3, pirq);
}
/* Put the PIR table in memory and checksum. */
return pirtable_end;
}

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@ -1,3 +1,22 @@
/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Advanced Micro Devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
@ -6,20 +25,15 @@
#include <arch/io.h> #include <arch/io.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h> #include <cpu/amd/lxdef.h>
#include "../../../southbridge/amd/cs5536/cs5536.h"
#include "chip.h" #include "chip.h"
#define DIVIL_LBAR_GPIO 0x5140000c
static void init_gpio() static void init_gpio()
{ {
msr_t msr; msr_t msr;
printk_debug("Initializing GPIO module...\n"); printk_debug("Checking GPIO module...\n");
// initialize the GPIO LBAR msr = rdmsr(MDD_LBAR_GPIO);
msr.lo = GPIO_BASE;
msr.hi = 0x0000f001;
wrmsr(DIVIL_LBAR_GPIO, msr);
msr = rdmsr(DIVIL_LBAR_GPIO);
printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo); printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
} }

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@ -0,0 +1,53 @@
/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <spd.h>
struct spd_entry {
unsigned int address;
unsigned int data;
};
/* Save space by using a short list of SPD values used by Geode LX Memory init */
/* 128MB */
const struct spd_entry spd_table [] =
{
{SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */
{SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */
{SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */
{SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */
{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x50}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
{SPD_REFRESH, 0x82}, /* Refresh rate/type */
{SPD_PRIMARY_SDRAM_WIDTH, 0x08}, /* SDRAM width (primary SDRAM) */
{SPD_NUM_BANKS_PER_SDRAM, 0x04}, /* SDRAM device attributes, number of banks on SDRAM device */
{SPD_ACCEPTABLE_CAS_LATENCIES, 0x1C}, /* SDRAM device attributes, CAS latency */
{SPD_MODULE_ATTRIBUTES, 0x20}, /* SDRAM module attributes */
{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xC0}, /* SDRAM device attributes, general */
{SPD_SDRAM_CYCLE_TIME_2ND, 0x60}, /* SDRAM cycle time (2nd highest CAS latency) */
{SPD_SDRAM_CYCLE_TIME_3RD, 0x75}, /* SDRAM cycle time (3rd highest CAS latency) */
{SPD_MIN_ROW_PRECHARGE_TIME, 0x3C}, /* Minimum row precharge time (Trp) */
{SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x28}, /* Minimum row active to row active (Trrd) */
{SPD_MIN_RAS_TO_CAS_DELAY, 0x3C}, /* Minimum RAS to CAS delay (Trcd) */
{SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x28}, /* Minimum RAS pulse width (Tras) */
{SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */
{SPD_CMD_SIGNAL_INPUT_HOLD_TIME, 0x60}, /* Command and address signal input hold time */
{SPD_tRC, 0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
{SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
};

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@ -3,14 +3,21 @@
target dbe61 target dbe61
mainboard artecgroup/dbe61 mainboard artecgroup/dbe61
# HACK to get the right TSC support.
option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use ## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
## (normal AND fallback images and payloads). ## (normal AND fallback images and payloads).
## leave 64k for vsa and 32K for video ROM ## leave 36k for vsa and 32K for video ROM
option ROM_SIZE = 1024*256 - 64*1024 - 32 * 1024 #option ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024
## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image, #No VGA for now
option ROM_SIZE = 1024*512 - 36*1024
# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
## not including any payload. ## not including any payload.
option ROM_IMAGE_SIZE=64*1024 option ROM_IMAGE_SIZE=64*1024
@ -21,7 +28,7 @@ option MAXIMUM_CONSOLE_LOGLEVEL = 11
romimage "fallback" romimage "fallback"
option USE_FALLBACK_IMAGE=1 option USE_FALLBACK_IMAGE=1
option LINUXBIOS_EXTRA_VERSION=".0Fallback" option LINUXBIOS_EXTRA_VERSION=".0Fallback"
payload /tmp/filo.elf payload ../payload.elf
end end
buildrom ./linuxbios.rom ROM_SIZE "fallback" buildrom ./dbe61.rom ROM_SIZE "fallback"