northbridge/amd/lx: Fix function setShadowRCONF

GCC 7.1 found an int-in-bool-context in northbridgeinit.c. The logical
`&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise
`&`.

Also fix off-by-one error with the bitmasks.

Change-Id: I7d7720121d4730254542372282f5561739e7214b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20808
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Iru Cai 2017-07-28 23:40:44 +08:00 committed by Patrick Georgi
parent 13a500a404
commit a0ad6e7873
1 changed files with 8 additions and 8 deletions

View File

@ -485,18 +485,18 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
shadowByte = (uint8_t) (shadowLo >> 16);
// load up D000 settings in edx.
for (bit = 8; (bit > 4); bit--) {
for (bit = 7; bit >= 4; bit--) {
msr.hi <<= 8;
msr.hi |= 1; // cache disable PCI/Shadow memory
if (shadowByte && (1 << bit))
if (shadowByte & (1 << bit))
msr.hi |= 0x20; // write serialize PCI memory
}
// load up C000 settings in eax.
for (; bit; bit--) {
for (; bit >= 0; bit--) {
msr.lo <<= 8;
msr.lo |= 1; // cache disable PCI/Shadow memory
if (shadowByte && (1 << bit))
if (shadowByte & (1 << bit))
msr.lo |= 0x20; // write serialize PCI memory
}
@ -505,18 +505,18 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
shadowByte = (uint8_t) (shadowLo >> 24);
// load up F000 settings in edx.
for (bit = 8; (bit > 4); bit--) {
for (bit = 7; bit >= 4; bit--) {
msr.hi <<= 8;
msr.hi |= 1; // cache disable PCI/Shadow memory
if (shadowByte && (1 << bit))
if (shadowByte & (1 << bit))
msr.hi |= 0x20; // write serialize PCI memory
}
// load up E000 settings in eax.
for (; bit; bit--) {
for (; bit >= 0; bit--) {
msr.lo <<= 8;
msr.lo |= 1; // cache disable PCI/Shadow memory
if (shadowByte && (1 << bit))
if (shadowByte & (1 << bit))
msr.lo |= 0x20; // write serialize PCI memory
}