northbridge/amd/lx: Fix function setShadowRCONF
GCC 7.1 found an int-in-bool-context in northbridgeinit.c. The logical `&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise `&`. Also fix off-by-one error with the bitmasks. Change-Id: I7d7720121d4730254542372282f5561739e7214b Signed-off-by: Iru Cai <mytbk920423@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20808 Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -485,18 +485,18 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
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shadowByte = (uint8_t) (shadowLo >> 16);
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// load up D000 settings in edx.
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for (bit = 8; (bit > 4); bit--) {
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for (bit = 7; bit >= 4; bit--) {
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msr.hi <<= 8;
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msr.hi |= 1; // cache disable PCI/Shadow memory
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if (shadowByte && (1 << bit))
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if (shadowByte & (1 << bit))
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msr.hi |= 0x20; // write serialize PCI memory
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}
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// load up C000 settings in eax.
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for (; bit; bit--) {
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for (; bit >= 0; bit--) {
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msr.lo <<= 8;
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msr.lo |= 1; // cache disable PCI/Shadow memory
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if (shadowByte && (1 << bit))
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if (shadowByte & (1 << bit))
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msr.lo |= 0x20; // write serialize PCI memory
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}
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@ -505,18 +505,18 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
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shadowByte = (uint8_t) (shadowLo >> 24);
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// load up F000 settings in edx.
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for (bit = 8; (bit > 4); bit--) {
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for (bit = 7; bit >= 4; bit--) {
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msr.hi <<= 8;
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msr.hi |= 1; // cache disable PCI/Shadow memory
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if (shadowByte && (1 << bit))
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if (shadowByte & (1 << bit))
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msr.hi |= 0x20; // write serialize PCI memory
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}
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// load up E000 settings in eax.
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for (; bit; bit--) {
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for (; bit >= 0; bit--) {
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msr.lo <<= 8;
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msr.lo |= 1; // cache disable PCI/Shadow memory
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if (shadowByte && (1 << bit))
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if (shadowByte & (1 << bit))
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msr.lo |= 0x20; // write serialize PCI memory
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}
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