device/pci_early: Drop some __SIMPLE_DEVICE__ use
The simple PCI config accessors are always available under names pci_s_[read|write]_configX. We have some use for PCI bridge configurations and resets in romstages, so expose them. Change-Id: Ia97a4e1f1b4c80b3dae800d80615bdc118414ed3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Kyösti Mälkki
parent
50b4f78344
commit
a0b366d550
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@ -11,64 +11,61 @@
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pci_type.h>
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#include <delay.h>
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static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge)
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void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge)
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{
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u16 reg16;
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/* First we reset the secondary bus. */
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reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
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reg16 |= (1 << 6); /* SRESET */
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pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
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/* Assume we don't have to wait here forever */
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/* Read back and clear reset bit. */
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reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
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reg16 &= ~(1 << 6); /* SRESET */
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pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
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reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
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reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
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pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
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}
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static void pci_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary)
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void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge)
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{
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u16 reg16;
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reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
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reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
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pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
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}
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void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary)
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{
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/* Disable config transaction forwarding. */
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pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
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pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
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pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
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pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
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/* Enable config transaction forwarding. */
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pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
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pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
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pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
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pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
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}
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static void pci_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size)
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static void pci_s_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size)
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{
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u16 reg16;
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/* Disable MMIO window behind the bridge. */
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reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
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reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
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pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10);
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pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
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pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10);
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if (!size)
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return;
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/* Enable MMIO window behind the bridge. */
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pci_write_config32(p2p_bridge, PCI_MEMORY_BASE,
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pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE,
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((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0));
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reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
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reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MEMORY;
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pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
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pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
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}
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void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
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static void pci_s_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
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{
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int timeout, ret = -1;
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@ -79,12 +76,14 @@ void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
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u8 dev = 0;
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/* Enable configuration and MMIO over bridge. */
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pci_bridge_reset_secondary(p2p_bridge);
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pci_bridge_set_secondary(p2p_bridge, secondary);
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pci_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size);
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pci_s_assert_secondary_reset(p2p_bridge);
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pci_s_deassert_secondary_reset(p2p_bridge);
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pci_s_bridge_set_secondary(p2p_bridge, secondary);
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pci_s_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size);
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for (timeout = 20000; timeout; timeout--) {
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u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID);
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pci_devfn_t dbg_dev = PCI_DEV(secondary, dev, 0);
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u32 id = pci_s_read_config32(dbg_dev, PCI_VENDOR_ID);
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if (id != 0 && id != 0xffffffff && id != 0xffff0001)
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break;
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udelay(10);
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@ -95,13 +94,13 @@ void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
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/* Disable MMIO window if we found no suitable device. */
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if (ret)
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pci_bridge_set_mmio(p2p_bridge, 0, 0);
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pci_s_bridge_set_mmio(p2p_bridge, 0, 0);
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/* Resource allocator will reconfigure bridges and secondary bus
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* number may change. Thus early device cannot reliably use config
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* transactions from here on, so we may as well disable them.
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*/
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pci_bridge_set_secondary(p2p_bridge, 0);
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pci_s_bridge_set_secondary(p2p_bridge, 0);
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}
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void pci_early_bridge_init(void)
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@ -112,7 +111,7 @@ void pci_early_bridge_init(void)
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pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE,
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CONFIG_EARLY_PCI_BRIDGE_FUNCTION);
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pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000);
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pci_s_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000);
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}
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/* FIXME: A lot of issues using the following, please avoid.
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@ -123,7 +122,7 @@ pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
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{
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for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
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unsigned int id;
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id = pci_read_config32(dev, 0);
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id = pci_s_read_config32(dev, 0);
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if (id == pci_id)
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return dev;
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}
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@ -139,7 +138,7 @@ pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
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for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
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unsigned int id;
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id = pci_read_config32(dev, 0);
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id = pci_s_read_config32(dev, 0);
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if (id == pci_id)
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return dev;
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}
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@ -116,8 +116,10 @@ struct msix_entry *pci_msix_get_table(struct device *dev);
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pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev);
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pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus);
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void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base,
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u32 mmio_size);
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void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge);
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void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge);
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void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary);
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int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base);
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static inline int pci_base_address_is_memory_space(unsigned int attr)
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