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device/pci_early: Drop some __SIMPLE_DEVICE__ use 

The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.

We have some use for PCI bridge configurations and
resets in romstages, so expose them.

Change-Id: Ia97a4e1f1b4c80b3dae800d80615bdc118414ed3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-09-26 22:33:51 +03:00
parent 50b4f78344
commit a0b366d550
2 changed files with 40 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

73
src/device/pci_early.c
View File

@ -11,64 +11,61 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#define __SIMPLE_DEVICE__
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_type.h> #include <device/pci_type.h>
#include <delay.h> #include <delay.h>
static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge)
{ {
u16 reg16; u16 reg16;
reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
/* First we reset the secondary bus. */ reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
reg16 |= (1 << 6); /* SRESET */
pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
/* Assume we don't have to wait here forever */
/* Read back and clear reset bit. */
reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
reg16 &= ~(1 << 6); /* SRESET */
pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
} }
static void pci_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary) void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge)
{
u16 reg16;
reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
}
void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary)
{ {
/* Disable config transaction forwarding. */ /* Disable config transaction forwarding. */
pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00); pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
/* Enable config transaction forwarding. */ /* Enable config transaction forwarding. */
pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary); pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
} }
static void pci_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size) static void pci_s_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size)
{ {
u16 reg16; u16 reg16;
/* Disable MMIO window behind the bridge. */ /* Disable MMIO window behind the bridge. */
reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY; reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10); pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10);
if (!size) if (!size)
return; return;
/* Enable MMIO window behind the bridge. */ /* Enable MMIO window behind the bridge. */
pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE,
((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0)); ((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0));
reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY; reg16 |= PCI_COMMAND_MEMORY;
pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
} }
void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size) static void pci_s_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
{ {
int timeout, ret = -1; int timeout, ret = -1;
@ -79,12 +76,14 @@ void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
u8 dev = 0; u8 dev = 0;
/* Enable configuration and MMIO over bridge. */ /* Enable configuration and MMIO over bridge. */
pci_bridge_reset_secondary(p2p_bridge); pci_s_assert_secondary_reset(p2p_bridge);
pci_bridge_set_secondary(p2p_bridge, secondary); pci_s_deassert_secondary_reset(p2p_bridge);
pci_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size); pci_s_bridge_set_secondary(p2p_bridge, secondary);
pci_s_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size);
for (timeout = 20000; timeout; timeout--) { for (timeout = 20000; timeout; timeout--) {
u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID); pci_devfn_t dbg_dev = PCI_DEV(secondary, dev, 0);
u32 id = pci_s_read_config32(dbg_dev, PCI_VENDOR_ID);
if (id != 0 && id != 0xffffffff && id != 0xffff0001) if (id != 0 && id != 0xffffffff && id != 0xffff0001)
break; break;
udelay(10); udelay(10);
@ -95,13 +94,13 @@ void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
/* Disable MMIO window if we found no suitable device. */ /* Disable MMIO window if we found no suitable device. */
if (ret) if (ret)
pci_bridge_set_mmio(p2p_bridge, 0, 0); pci_s_bridge_set_mmio(p2p_bridge, 0, 0);
/* Resource allocator will reconfigure bridges and secondary bus /* Resource allocator will reconfigure bridges and secondary bus
* number may change. Thus early device cannot reliably use config * number may change. Thus early device cannot reliably use config
* transactions from here on, so we may as well disable them. * transactions from here on, so we may as well disable them.
*/ */
pci_bridge_set_secondary(p2p_bridge, 0); pci_s_bridge_set_secondary(p2p_bridge, 0);
} }
void pci_early_bridge_init(void) void pci_early_bridge_init(void)
@ -112,7 +111,7 @@ void pci_early_bridge_init(void)
pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE,
CONFIG_EARLY_PCI_BRIDGE_FUNCTION); CONFIG_EARLY_PCI_BRIDGE_FUNCTION);
pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000); pci_s_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000);
} }
/* FIXME: A lot of issues using the following, please avoid. /* FIXME: A lot of issues using the following, please avoid.
@ -123,7 +122,7 @@ pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
{ {
for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
unsigned int id; unsigned int id;
id = pci_read_config32(dev, 0); id = pci_s_read_config32(dev, 0);
if (id == pci_id) if (id == pci_id)
return dev; return dev;
} }
@ -139,7 +138,7 @@ pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
for (; dev <= last; dev += PCI_DEV(0, 0, 1)) { for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
unsigned int id; unsigned int id;
id = pci_read_config32(dev, 0); id = pci_s_read_config32(dev, 0);
if (id == pci_id) if (id == pci_id)
return dev; return dev;
} }

6
src/include/device/pci.h
View File

@ -116,8 +116,10 @@ struct msix_entry *pci_msix_get_table(struct device *dev);
pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev); pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev);
pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus); pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus);
void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge);
u32 mmio_size); void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge);
void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary);
int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base);
static inline int pci_base_address_is_memory_space(unsigned int attr) static inline int pci_base_address_is_memory_space(unsigned int attr)