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soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config 

The PCI config space of the SMBus device has a secondary mapping as an
ACPIMMIO bank. Since the PCI device is on bus 0, it's already available
early in boot after the enable_pci_mmconf call, so there's no need to
use the ACPIMMIO mapping instead of the PCI config space mapping.
Verstage on PSP could theoretically access the PCI config space via the
0xcf8/0xcfc register pair, but since verstage on PSP doesn't have the
ACPIMMIO mapping anyway, we won't loose any functionality here.

Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Kyösti Mälkki 2020-06-18 23:04:33 +03:00 committed by Felix Held
parent a21a738cce
commit a0b92b019f
2 changed files with 0 additions and 32 deletions
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1
src/soc/amd/common/block/acpimmio/mmio_util.c
View File

@ -21,7 +21,6 @@ DECLARE_ACPIMMIO(acpimmio_gpio0, GPIO0);
DECLARE_ACPIMMIO(acpimmio_misc, MISC);
#if ENV_X86
DECLARE_ACPIMMIO(acpimmio_sm_pci, SM_PCI);
DECLARE_ACPIMMIO(acpimmio_gpio_100, GPIO_100);
DECLARE_ACPIMMIO(acpimmio_smi, SMI);
DECLARE_ACPIMMIO(acpimmio_pmio, PMIO);

31
src/soc/amd/common/block/include/amdblocks/acpimmio.h
View File

@ -56,7 +56,6 @@
#endif
extern uint8_t *MAYBE_CONST acpimmio_gpio_100;
extern uint8_t *MAYBE_CONST acpimmio_sm_pci;
extern uint8_t *MAYBE_CONST acpimmio_smi;
extern uint8_t *MAYBE_CONST acpimmio_pmio;
extern uint8_t *MAYBE_CONST acpimmio_pmio2;
@ -103,36 +102,6 @@ void pm_io_write32(uint8_t reg, uint32_t value);
/* Print source of last reset */
void fch_print_pmxc0_status(void);
static inline uint8_t sm_pci_read8(uint8_t reg)
{
return read8(acpimmio_sm_pci + reg);
}
static inline uint16_t sm_pci_read16(uint8_t reg)
{
return read16(acpimmio_sm_pci + reg);
}
static inline uint32_t sm_pci_read32(uint8_t reg)
{
return read32(acpimmio_sm_pci + reg);
}
static inline void sm_pci_write8(uint8_t reg, uint8_t value)
{
write8(acpimmio_sm_pci + reg, value);
}
static inline void sm_pci_write16(uint8_t reg, uint16_t value)
{
write16(acpimmio_sm_pci + reg, value);
}
static inline void sm_pci_write32(uint8_t reg, uint32_t value)
{
write32(acpimmio_sm_pci + reg, value);
}
static inline uint8_t smi_read8(uint8_t reg)
{
return read8(acpimmio_smi + reg);