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nb/intel/x4x: Drop unused first array index 

The first RCOMP group (data) is programmed differently, and has its own
tables. Remove the unused first index from the other tables, and adjust
the loop bound accordingly. Cosmetics are cleaned up in a follow-up.

Tested on Asus P5QL PRO (DDR2), still boots.

Change-Id: I3010acbd00f762c91aebeaf1625ed7543b14bf74
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2021-01-13 17:50:27 +01:00 committed by Patrick Georgi
parent 244391a075
commit a0b97f3743
1 changed files with 22 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
src/northbridge/intel/x4x/raminit_ddr23.c
View File

@ -1039,34 +1039,34 @@ static void prog_rcomp(struct sysinfo *s)
u8 i, j, k, reg8;
const u32 ddr2_x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A,
0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D };
const u16 ddr2_x378[6] = { 0, 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 };
const u32 ddr2_x382[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 };
const u32 ddr2_x386[6] = { 0, 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 };
const u32 ddr2_x38a[6] = { 0, 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 };
const u32 ddr2_x38e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 };
const u32 ddr2_x392[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 };
const u32 ddr2_x396[6] = { 0, 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 };
const u32 ddr2_x39a[6] = { 0, 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 };
const u32 ddr2_x39e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 };
const u16 ddr2_x378[5] = { 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 };
const u32 ddr2_x382[5] = { 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 };
const u32 ddr2_x386[5] = { 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 };
const u32 ddr2_x38a[5] = { 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 };
const u32 ddr2_x38e[5] = { 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 };
const u32 ddr2_x392[5] = { 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 };
const u32 ddr2_x396[5] = { 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 };
const u32 ddr2_x39a[5] = { 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 };
const u32 ddr2_x39e[5] = { 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 };
const u32 ddr3_x32a[8] = {0x06060606, 0x06060606, 0x0b090807, 0x12110f0d,
0x06060606, 0x08070606, 0x0d0b0a09, 0x16161511};
const u16 ddr3_x378[6] = {0, 0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666};
const u32 ddr3_x382[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
const u32 ddr3_x386[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
const u32 ddr3_x38a[6] = {0, 0x06060605, 0x07060504, 0x07060504, 0x34343434, 0x34343434};
const u32 ddr3_x38e[6] = {0, 0x09080707, 0x09090808, 0x09090808, 0x34343434, 0x34343434};
const u32 ddr3_x392[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
const u32 ddr3_x396[6] = {0, 0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
const u32 ddr3_x39a[6] = {0, 0x07060606, 0x08070605, 0x08070605, 0x34343434, 0x34343434};
const u32 ddr3_x39e[6] = {0, 0x09090807, 0x0b0b0a09, 0x0b0b0a09, 0x34343434, 0x34343434};
const u16 ddr3_x378[5] = {0xbbbb, 0x6666, 0x6666, 0x6666, 0x6666};
const u32 ddr3_x382[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
const u32 ddr3_x386[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
const u32 ddr3_x38a[5] = {0x06060605, 0x07060504, 0x07060504, 0x34343434, 0x34343434};
const u32 ddr3_x38e[5] = {0x09080707, 0x09090808, 0x09090808, 0x34343434, 0x34343434};
const u32 ddr3_x392[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
const u32 ddr3_x396[5] = {0x05050505, 0x04040404, 0x04040404, 0x34343434, 0x34343434};
const u32 ddr3_x39a[5] = {0x07060606, 0x08070605, 0x08070605, 0x34343434, 0x34343434};
const u32 ddr3_x39e[5] = {0x09090807, 0x0b0b0a09, 0x0b0b0a09, 0x34343434, 0x34343434};
const u16 *x378;
const u32 *x32a, *x382, *x386, *x38a, *x38e;
const u32 *x392, *x396, *x39a, *x39e;
const u16 addr[6] = { 0x31c, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c };
u8 bit[6] = { 0, 0, 1, 1, 0, 0 };
const u16 addr[5] = { 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c };
u8 bit[5] = { 0, 1, 1, 0, 0 };
if (s->spd_type == DDR2) {
x32a = ddr2_x32a;
@ -1109,10 +1109,8 @@ static void prog_rcomp(struct sysinfo *s)
MCHBAR8_AND_OR(0x400*i + 0x31c, ~1, 0);
/* Now program the other RCOMP groups */
for (j = 0; j < 6; j++) {
if (j == 0) {
continue;
} else {
for (j = 0; j < ARRAY_SIZE(addr); j++) {
{
MCHBAR16_AND_OR(0x400*i + addr[j],
~0xf000, 0xa000);
MCHBAR16_AND_OR(0x400*i + addr[j] + 4,