mb/google: AMD: move tpm_tis to AMD common code

It moves cr50_plat_irq_status() to common code and adds Kconfig
option to specify GPIO used for interrupt.

BUG=b:277787305
TEST=Build all affected platform and confirm using right GPIO
number. Tested on Skyrim.

Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

src/mainboard/google/guybrush/Kconfig

@@ -95,6 +95,11 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x50
 
+config GSC_IRQ_GPIO
+	int
+	default 3 if BOARD_GOOGLE_GUYBRUSH
+	default 85
+
 config AMDFW_CONFIG_FILE
 	string
 	default "src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg"

src/mainboard/google/guybrush/variants/baseboard/Makefile.inc

@@ -2,14 +2,11 @@ bootblock-y += gpio.c
 bootblock-y += helpers.c
 
 romstage-y += helpers.c
-romstage-y += tpm_tis.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
 ramstage-y += helpers.c
-ramstage-y += tpm_tis.c
 
 verstage-y += gpio.c
-verstage-y += tpm_tis.c
 
 smm-y += gpio.c

src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c

@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <boardid.h>
-#include <drivers/tpm/cr50.h>
-#include <gpio.h>
-
-int cr50_plat_irq_status(void)
-{
-	gpio_t irq_gpio = GPIO_85;
-	uint32_t board_ver = board_id();
-
-	if (CONFIG(BOARD_GOOGLE_GUYBRUSH) || (CONFIG(BOARD_GOOGLE_NIPPERKIN) && board_ver == 1))
-		irq_gpio = GPIO_3;
-
-	return gpio_interrupt_status(irq_gpio);
-}

src/mainboard/google/guybrush/variants/nipperkin/Makefile.inc

@@ -5,6 +5,10 @@ romstage-y += gpio.c
 ramstage-y += gpio.c
 verstage-y += gpio.c
 
+romstage-y += tpm_tis.c
+ramstage-y += tpm_tis.c
+verstage-y += tpm_tis.c
+
 bootblock-y += variant.c
 romstage-y += variant.c
 ramstage-y += variant.c

src/mainboard/google/guybrush/variants/nipperkin/tpm_tis.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <boardid.h>
+#include <gpio.h>
+#include <drivers/tpm/cr50.h>
+
+gpio_t cr50_override_gpio(gpio_t irq)
+{
+	if (board_id() == 1)
+		return GPIO_3;
+	else
+		return irq;
+}

src/mainboard/google/kahlee/Kconfig

@@ -116,6 +116,10 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x50
 
+config GSC_IRQ_GPIO
+	int
+	default 9
+
 config USE_OEM_BIN
 	bool "Add an oem.bin file"
 	help

src/mainboard/google/kahlee/variants/baseboard/Makefile.inc

@@ -3,16 +3,12 @@
 bootblock-y += gpio.c
 bootblock-y += OemCustomize.c
 
-verstage-y += tpm_tis.c
-
 romstage-y += OemCustomize.c
 romstage-y += gpio.c
 romstage-y += memory.c
-romstage-y += tpm_tis.c
 
 ramstage-y += gpio.c
 ramstage-y += mainboard.c
-ramstage-y += tpm_tis.c
 
 # Add OEM ID table
 ifeq ($(CONFIG_USE_OEM_BIN),y)

src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <drivers/tpm/cr50.h>
-#include <gpio.h>
-#include <variant/gpio.h>
-
-int cr50_plat_irq_status(void)
-{
-	return gpio_interrupt_status(GPIO_9);
-}

src/mainboard/google/myst/Kconfig

@@ -44,6 +44,10 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x50
 
+config GSC_IRQ_GPIO
+	int
+	default 84
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
 

src/mainboard/google/myst/variants/baseboard/Makefile.inc

@@ -2,12 +2,9 @@ bootblock-y += gpio.c
 
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += gpio.c
-ramstage-y += tpm_tis.c
 
 romstage-y += gpio.c
-romstage-y += tpm_tis.c
 
-verstage-y += tpm_tis.c
 verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += gpio.c
 
 smm-y += smihandler.c

src/mainboard/google/myst/variants/baseboard/tpm_tis.c

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <drivers/tpm/cr50.h>
-#include <gpio.h>
-
-int cr50_plat_irq_status(void)
-{
-	return gpio_interrupt_status(GPIO_84);
-}

src/mainboard/google/skyrim/Kconfig

@@ -60,6 +60,10 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x50
 
+config GSC_IRQ_GPIO
+	int
+	default 18
+
 config AMDFW_CONFIG_FILE
 	string
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/amdfw.cfg"

src/mainboard/google/skyrim/variants/baseboard/Makefile.inc

@@ -1,12 +1,9 @@
 bootblock-y += gpio.c
 
 romstage-y += gpio.c
-romstage-y += tpm_tis.c
 
 ramstage-y += gpio.c
-ramstage-y += tpm_tis.c
 
-verstage-y += tpm_tis.c
 verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += gpio.c
 
 smm-y += gpio.c

src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <drivers/tpm/cr50.h>
-#include <gpio.h>
-
-int cr50_plat_irq_status(void)
-{
-	return gpio_interrupt_status(GPIO_18);
-}

src/mainboard/google/zork/Kconfig

@@ -138,6 +138,10 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x50
 
+config GSC_IRQ_GPIO
+	int
+	default 3
+
 config VARIANT_SUPPORTS_PRE_V3_SCHEMATICS
 	bool
 	default y if BOARD_GOOGLE_TREMBYLE

src/mainboard/google/zork/variants/baseboard/Makefile.inc

@@ -2,9 +2,6 @@
 
 all-y += helpers.c
 
-verstage-y += tpm_tis.c
-romstage-y += tpm_tis.c
-ramstage-y += tpm_tis.c
 ramstage-y += ramstage_common.c
 
 # Add OEM ID table

src/mainboard/google/zork/variants/baseboard/tpm_tis.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <drivers/tpm/cr50.h>
-#include <gpio.h>
-#include <variant/gpio.h>
-
-int cr50_plat_irq_status(void)
-{
-	return gpio_interrupt_status(GPIO_3);
-}

src/soc/amd/common/block/gpio/Kconfig

@@ -18,3 +18,9 @@ config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE
 	  code.
 
 endif # SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
+
+config GSC_IRQ_GPIO
+	int
+	help
+	  gpio_interrupt_status() is used to provide interrupt status to TPM layer.
+	  This option specifies the GPIO number.

src/soc/amd/common/block/gpio/Makefile.inc

@@ -4,4 +4,8 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS),y)
 all-y += gpio.c
 smm-y += gpio.c
 
+romstage-$(CONFIG_TPM_GOOGLE) += tpm_tis.c
+ramstage-$(CONFIG_TPM_GOOGLE) += tpm_tis.c
+verstage-$(CONFIG_TPM_GOOGLE) += tpm_tis.c
+
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS

src/soc/amd/common/block/gpio/tpm_tis.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <drivers/tpm/cr50.h>
+#include <gpio.h>
+
+__weak gpio_t cr50_override_gpio(gpio_t irq)
+{
+	return irq;
+}
+
+int cr50_plat_irq_status(void)
+{
+	gpio_t irq_gpio = CONFIG_GSC_IRQ_GPIO;
+
+	irq_gpio = cr50_override_gpio(irq_gpio);
+
+	return gpio_interrupt_status(irq_gpio);
+}

src/soc/amd/common/block/include/amdblocks/gpio.h

@@ -92,4 +92,7 @@ void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items)
 void gpio_save_pin_registers(gpio_t gpio, struct soc_amd_gpio_register_save *save);
 void gpio_restore_pin_registers(gpio_t gpio, struct soc_amd_gpio_register_save *save);
 
+/* Overrides Kconfig GPIO number */
+gpio_t cr50_override_gpio(gpio_t irq);
+
 #endif /* AMD_BLOCK_GPIO_BANKS_H */