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mb/google/brya: Configure TCSS OC pins for brya 

TCSS OC pins has not been correctly configured for brya.
This patch fills the value from devicetree to correct the OC pins
mapping

BUG=b:184653645
BRANCH=None
TEST=check if UPD value has been reflected correctly

Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Maulik V Vaghela 2021-04-14 14:08:16 +05:30 committed by Patrick Georgi
parent 6935350ad6
commit a0d48096ad
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/brya/variants/baseboard/devicetree.cb
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@ -47,6 +47,10 @@ chip soc/intel/alderlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)"
register "SerialIoI2cMode" = "{ register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci,