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soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` config 

List of changes:

1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.

Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2022-01-03 18:07:13 +00:00
parent 98ce39dce4
commit a0d9ad322f
37 changed files with 48 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/51nb/x210/devicetree.cb
View File

@ -47,7 +47,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

3
src/mainboard/asrock/h110m/Kconfig
View File

@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS
select RT8168_SET_LED_MODE
select MAINBOARD_HAS_LPC_TPM
config DISABLE_HECI1_AT_PRE_BOOT
default y
config MAINBOARD_DIR
default "asrock/h110m"

3
src/mainboard/asrock/h110m/devicetree.cb
View File

@ -101,9 +101,6 @@ chip soc/intel/skylake
device pci 15.3 off end # I2C #3
device pci 16.0 on # Management Engine Interface 1
subsystemid 0x1849 0xa131
# FIXME: does not match devicetree!
register "HeciEnabled" = "0"
end
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R

4
src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
View File

@ -60,9 +60,7 @@ chip soc/intel/skylake
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left
end
device ref thermal on end
device ref heci1 on
register "HeciEnabled" = "1"
end
device ref heci1 on end
device ref sata on
register "SataSalpSupport" = "0"
# Ports

3
src/mainboard/facebook/monolith/Kconfig
View File

@ -13,6 +13,9 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_GMA_HAVE_VBT
select VPD
config DISABLE_HECI1_AT_PRE_BOOT
default y
config CBFS_SIZE
default 0x00900000

2
src/mainboard/facebook/monolith/devicetree.cb
View File

@ -36,7 +36,6 @@ chip soc/intel/skylake
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
register "HeciEnabled" = "0"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
@ -224,6 +223,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 16.0 on end # Management Engine Interface 1
device pci 17.0 on end # SATA
device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN
device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210

3
src/mainboard/google/eve/Kconfig
View File

@ -24,6 +24,9 @@ config BOARD_SPECIFIC_OPTIONS
select SYSTEM_TYPE_CONVERTIBLE
select HAVE_SPD_IN_CBFS
config DISABLE_HECI1_AT_PRE_BOOT
default y
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select HAS_RECOVERY_MRC_CACHE

1
src/mainboard/google/eve/devicetree.cb
View File

@ -43,7 +43,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

3
src/mainboard/google/fizz/Kconfig
View File

@ -24,6 +24,9 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ
select RT8168_SUPPORT_LEGACY_VPD_MAC
select RT8168_SET_LED_MODE
config DISABLE_HECI1_AT_PRE_BOOT
default y
config BOARD_GOOGLE_FIZZ
select BOARD_GOOGLE_BASEBOARD_FIZZ

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -74,7 +74,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

3
src/mainboard/google/glados/Kconfig
View File

@ -21,6 +21,9 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS
select SOC_INTEL_SKYLAKE
select SYSTEM_TYPE_LAPTOP
config DISABLE_HECI1_AT_PRE_BOOT
default y
config BOARD_GOOGLE_ASUKA
select BOARD_GOOGLE_BASEBOARD_GLADOS
select DRIVERS_GENERIC_MAX98357A

1
src/mainboard/google/glados/devicetree.cb
View File

@ -42,7 +42,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "4" # 4s

3
src/mainboard/google/poppy/Kconfig
View File

@ -99,6 +99,9 @@ config BOARD_GOOGLE_SORAKA
if BOARD_GOOGLE_BASEBOARD_POPPY
config DISABLE_HECI1_AT_PRE_BOOT
default y
config CHROMEOS_WIFI_SAR
bool
depends on CHROMEOS

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -50,7 +50,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -37,7 +37,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -43,7 +43,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -50,7 +50,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

3
src/mainboard/hp/280_g2/Kconfig
View File

@ -16,6 +16,9 @@ config BOARD_SPECIFIC_OPTIONS
select SPD_READ_BY_WORD
select SUPERIO_ITE_COMMON_PRE_RAM
config DISABLE_HECI1_AT_PRE_BOOT
default y
config MAINBOARD_DIR
default "hp/280_g2"

3
src/mainboard/intel/kblrvp/Kconfig
View File

@ -31,6 +31,9 @@ config BOARD_INTEL_KBLRVP11
if BOARD_INTEL_KBLRVP_COMMON
config DISABLE_HECI1_AT_PRE_BOOT
default y
config VBOOT
select VBOOT_LID_SWITCH

1
src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
View File

@ -20,7 +20,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "HeciEnabled" = "0"
register "IoBufferOwnership" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"

3
src/mainboard/intel/kunimitsu/Kconfig
View File

@ -21,6 +21,9 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_SKYLAKE
select HAVE_SPD_IN_CBFS
config DISABLE_HECI1_AT_PRE_BOOT
default y
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_LID_SWITCH

1
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -25,7 +25,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch

3
src/mainboard/intel/saddlebrook/Kconfig
View File

@ -16,6 +16,9 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_CMOS_DEFAULT
select MAINBOARD_USES_IFD_GBE_REGION
config DISABLE_HECI1_AT_PRE_BOOT
default y
config MAINBOARD_DIR
default "intel/saddlebrook"

3
src/mainboard/kontron/bsl6/Kconfig
View File

@ -15,6 +15,9 @@ config BOARD_KONTRON_BSL6_COMMON
select MAINBOARD_HAS_LIBGFXINIT
select DRIVERS_I2C_NCT7802Y
config DISABLE_HECI1_AT_PRE_BOOT
default y
config BOARD_KONTRON_BSL6
select BOARD_KONTRON_BSL6_COMMON
select HAVE_ACPI_RESUME

1
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -46,7 +46,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

1
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -34,7 +34,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"
register "IslVrCmd" = "2"
register "PmConfigSlpS3MinAssert" = "2" # 50ms

3
src/mainboard/purism/librem_skl/Kconfig
View File

@ -18,6 +18,9 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL
if BOARD_PURISM_BASEBOARD_LIBREM_SKL
config DISABLE_HECI1_AT_PRE_BOOT
default y
config VARIANT_DIR
default "librem13" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4
default "librem15" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4

1
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -52,7 +52,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -31,7 +31,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "1" # 1s

3
src/mainboard/supermicro/x11-lga1151-series/Kconfig
View File

@ -18,6 +18,9 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
config DISABLE_HECI1_AT_PRE_BOOT
default y
config MAINBOARD_FAMILY
string
default "Supermicro_X11_LGA1151_SERIES"

3
src/mainboard/system76/kbl-u/Kconfig
View File

@ -18,6 +18,9 @@ config BOARD_SPECIFIC_OPTIONS
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
config DISABLE_HECI1_AT_PRE_BOOT
default y
config MAINBOARD_DIR
default "system76/kbl-u"

4
src/soc/intel/skylake/chip.c
View File

@ -410,11 +410,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
tconfig->PowerLimit4 = 0;
/*
* To disable HECI, the Psf needs to be left unlocked
* by FSP till end of post sequence. Based on the devicetree
* by FSP till end of post sequence. Based on the config
* setting, we set the appropriate PsfUnlock policy in FSP,
* do the changes and then lock it back in coreboot during finalize.
*/
tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0;
tconfig->PchSbAccessUnlock = CONFIG(DISABLE_HECI1_AT_PRE_BOOT);
const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
tconfig->PchLockDownBiosInterface = lockdown_by_fsp;

5
src/soc/intel/skylake/chip.h
View File

@ -395,11 +395,6 @@ struct soc_intel_skylake_config {
* 3 = GT unsliced, 4 = GT sliced
*/
struct vr_config domain_vr_config[NUM_VR_DOMAINS];
/*
* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS
*/
u8 HeciEnabled;
/*
* Enable VR specific mailbox command

8
src/soc/intel/skylake/finalize.c
View File

@ -44,15 +44,11 @@ static void pch_disable_heci(void)
static void pch_finalize_script(struct device *dev)
{
config_t *config;
tco_lockdown();
/* Display me status before we hide it */
intel_me_status();
config = config_of(dev);
/*
* Set low maximum temp value used for dynamic thermal sensor
* shutdown consideration.
@ -62,8 +58,8 @@ static void pch_finalize_script(struct device *dev)
*/
pch_thermal_configuration();
/* we should disable Heci1 based on the devicetree policy */
if (config->HeciEnabled == 0)
/* we should disable Heci1 based on the config */
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
pch_disable_heci();
/* Hide p2sb device as the OS must not change BAR0. */