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mb/google/brya: Lock PCH WP pin in brask and brya baseboards 

This applies a configuration lock to the PCH write protect GPIO for
all brya and brask variants.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-01-31 23:30:55 +05:30
parent abac030662
commit a0dd454115
2 changed files with 2 additions and 3 deletions
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2
src/mainboard/google/brya/variants/baseboard/brask/gpio.c
View File

@ -189,7 +189,7 @@ static const struct pad_config gpio_table[] = {
/* E14 : DDSP_HPDA ==> SOC_DP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
/* E16 : RSVD_TP ==> CLKREQ_8 */
PAD_NC(GPP_E16, NONE),
/* E17 : THC0_SPI1_INT# ==> TP102 */

3
src/mainboard/google/brya/variants/baseboard/brya/gpio.c
View File

@ -188,7 +188,7 @@ static const struct pad_config gpio_table[] = {
/* E14 : DDSP_HPDA ==> SOC_EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG),
/* E16 : RSVD_TP ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_E16, 1, DEEP),
/* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */
@ -458,7 +458,6 @@ const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
}
static struct gpio_lock_config lockable_brya_gpios[] = {
{ GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */
{ GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */
{ GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */
{ GPP_F12, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D0_FPMCU_D1_R */