soc/intel/cannonlake: Enable Energy/Performance Bias control

Set POWER_CTL MSR bit 18 to enable Energy/Performance Bias control.

TEST=Boot and verify EPB is enabled in coreboot log:

 cpu: energy policy set to 6

Change-Id: Ibd1db77b5b63cb6e2b0ad9d2f79caa2f3b576ead
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/cannonlake/cpu.c

@@ -51,6 +51,7 @@ static void configure_misc(void)
 	/* Enable PROCHOT */
 	msr = rdmsr(MSR_POWER_CTL);
 	msr.lo |= (1 << 0);	/* Enable Bi-directional PROCHOT as an input */
+	msr.lo |= (1 << 18);	/* Enable Energy/Performance Bias control */
 	msr.lo |= (1 << 23);	/* Lock it */
 	wrmsr(MSR_POWER_CTL, msr);
 }