slippy: Prepare LPC IO decode ranges for EC

- 0x200-0x208 for host command window
- 0x800-0x8ff for host command arguments and parameters
- 0x900-0x9ff for exported EC memory map

Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49755
Reviewed-on: http://review.coreboot.org/4151
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

src/mainboard/google/slippy/devicetree.cb

@@ -41,6 +41,10 @@ chip northbridge/intel/haswell
 			register "pirqg_routing" = "0x80"
 			register "pirqh_routing" = "0x80"
 
+			# EC range is 0x800-0x9ff
+			register "gen1_dec" = "0x00fc0801"
+			register "gen2_dec" = "0x00fc0901"
+
 			register "alt_gp_smi_en" = "0x0000"
 			register "gpe0_en_1" = "0x00000000"
 			# EC_SCI is GPIO36

src/southbridge/intel/lynxpoint/early_pch.c

@@ -102,7 +102,7 @@ static void pch_enable_lpc(void)
 	pci_write_config16(dev, LPC_IO_DEC, 0x0010);
 
 	/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */
-	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN |
+	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
 		COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
 	pci_write_config16(dev, LPC_EN, lpc_config);
 }