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soc/intel/common: Only touch Time Window Tau bits in supported SoCs 

The Time Window Tau bits are only supported by Comet Lake/Cannon Lake
onwards, so skip setting those bits for earlier SoCs.

Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Tim Wawrzynczak 2020-07-01 09:32:18 -06:00
parent 7b2f503038
commit a1061639d2
1 changed files with 9 additions and 1 deletions
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10
src/soc/intel/common/block/cpu/cpulib.c
View File

@ -272,9 +272,17 @@ void configure_tcc_thermal_target(void)
wrmsr(MSR_TEMPERATURE_TARGET, msr); wrmsr(MSR_TEMPERATURE_TARGET, msr);
} }
msr = rdmsr(MSR_TEMPERATURE_TARGET); /*
* SoCs prior to Comet Lake/Cannon Lake do not support the time window
* bits, so return early.
*/
if (CONFIG(SOC_INTEL_APOLLOLAKE) || CONFIG(SOC_INTEL_SKYLAKE) ||
CONFIG(SOC_INTEL_KABYLAKE) || CONFIG(SOC_INTEL_BRASWELL) ||
CONFIG(SOC_INTEL_BROADWELL))
return;
/* Time Window Tau Bits [6:0] */ /* Time Window Tau Bits [6:0] */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
msr.lo &= ~0x7f; msr.lo &= ~0x7f;
msr.lo |= 0xe6; /* setting 100ms thermal time window */ msr.lo |= 0xe6; /* setting 100ms thermal time window */
wrmsr(MSR_TEMPERATURE_TARGET, msr); wrmsr(MSR_TEMPERATURE_TARGET, msr);