soc/amd/stoneyridge: Hook up device_operations in chipset.cb

This removes the need for a lot of boilerplate code in the soc code to
hook up device_operations to devices.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id668587e1b747c28207b213b985204b7a961a631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68410
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2022-10-13 16:32:23 +02:00
parent 97a86734d2
commit a11b472fd3
3 changed files with 14 additions and 44 deletions

View File

@ -18,10 +18,7 @@
#include "chip.h"
/* Supplied by i2c.c */
extern struct device_operations soc_amd_i2c_mmio_ops;
struct device_operations cpu_bus_ops = {
struct device_operations stoneyridge_cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.init = mp_cpu_bus_init,
@ -90,7 +87,7 @@ const char *soc_acpi_name(const struct device *dev)
}
};
static struct device_operations pci_domain_ops = {
struct device_operations stoneyridge_pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = domain_enable_resources,
@ -98,36 +95,6 @@ static struct device_operations pci_domain_ops = {
.acpi_name = soc_acpi_name,
};
static void set_mmio_dev_ops(struct device *dev)
{
switch (dev->path.mmio.addr) {
case APU_I2C0_BASE:
case APU_I2C1_BASE:
case APU_I2C2_BASE:
case APU_I2C3_BASE:
dev->ops = &soc_amd_i2c_mmio_ops;
break;
}
}
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
switch (dev->path.type) {
case DEVICE_PATH_DOMAIN:
dev->ops = &pci_domain_ops;
break;
case DEVICE_PATH_CPU_CLUSTER:
dev->ops = &cpu_bus_ops;
break;
case DEVICE_PATH_MMIO:
set_mmio_dev_ops(dev);
break;
default:
break;
}
}
static void soc_init(void *chip_info)
{
fch_init(chip_info);
@ -141,7 +108,6 @@ static void soc_final(void *chip_info)
struct chip_operations soc_amd_stoneyridge_ops = {
CHIP_NAME("AMD StoneyRidge SOC")
.enable_dev = enable_dev,
.init = soc_init,
.final = soc_final
};

View File

@ -2,8 +2,10 @@
chip soc/amd/stoneyridge
device cpu_cluster 0 on
ops stoneyridge_cpu_bus_ops
end
device domain 0 on
ops stoneyridge_pci_domain_ops
device pci 00.0 alias gnb on end
device pci 00.2 alias iommu off end
device pci 01.0 alias gfx off end # internal GPU
@ -37,8 +39,8 @@ chip soc/amd/stoneyridge
device pci 18.5 alias ht_5 on end
end
device mmio 0xfedc2000 alias i2c_0 off end
device mmio 0xfedc3000 alias i2c_1 off end
device mmio 0xfedc4000 alias i2c_2 off end
device mmio 0xfedc5000 alias i2c_3 off end
device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
end

View File

@ -2,8 +2,10 @@
chip soc/amd/stoneyridge
device cpu_cluster 0 on
ops stoneyridge_cpu_bus_ops
end
device domain 0 on
ops stoneyridge_pci_domain_ops
device pci 00.0 alias gnb on end
device pci 00.2 alias iommu off end
device pci 01.0 alias gfx off end # internal GPU
@ -31,8 +33,8 @@ chip soc/amd/stoneyridge
device pci 18.5 alias ht_5 on end
end
device mmio 0xfedc2000 alias i2c_0 off end
device mmio 0xfedc3000 alias i2c_1 off end
device mmio 0xfedc4000 alias i2c_2 off end
device mmio 0xfedc5000 alias i2c_3 off end
device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
end