soc/amd/stoneyridge: Hook up device_operations in chipset.cb
This removes the need for a lot of boilerplate code in the soc code to hook up device_operations to devices. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id668587e1b747c28207b213b985204b7a961a631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68410 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -18,10 +18,7 @@
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#include "chip.h"
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/* Supplied by i2c.c */
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extern struct device_operations soc_amd_i2c_mmio_ops;
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struct device_operations cpu_bus_ops = {
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struct device_operations stoneyridge_cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = mp_cpu_bus_init,
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@ -90,7 +87,7 @@ const char *soc_acpi_name(const struct device *dev)
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}
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};
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static struct device_operations pci_domain_ops = {
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struct device_operations stoneyridge_pci_domain_ops = {
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.read_resources = domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = domain_enable_resources,
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@ -98,36 +95,6 @@ static struct device_operations pci_domain_ops = {
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.acpi_name = soc_acpi_name,
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};
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static void set_mmio_dev_ops(struct device *dev)
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{
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switch (dev->path.mmio.addr) {
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case APU_I2C0_BASE:
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case APU_I2C1_BASE:
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case APU_I2C2_BASE:
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case APU_I2C3_BASE:
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dev->ops = &soc_amd_i2c_mmio_ops;
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break;
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}
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}
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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switch (dev->path.type) {
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case DEVICE_PATH_DOMAIN:
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dev->ops = &pci_domain_ops;
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break;
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case DEVICE_PATH_CPU_CLUSTER:
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dev->ops = &cpu_bus_ops;
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break;
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case DEVICE_PATH_MMIO:
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set_mmio_dev_ops(dev);
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break;
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default:
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break;
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}
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}
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static void soc_init(void *chip_info)
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{
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fch_init(chip_info);
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@ -141,7 +108,6 @@ static void soc_final(void *chip_info)
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struct chip_operations soc_amd_stoneyridge_ops = {
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CHIP_NAME("AMD StoneyRidge SOC")
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.enable_dev = enable_dev,
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.init = soc_init,
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.final = soc_final
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};
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@ -2,8 +2,10 @@
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chip soc/amd/stoneyridge
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device cpu_cluster 0 on
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ops stoneyridge_cpu_bus_ops
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end
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device domain 0 on
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ops stoneyridge_pci_domain_ops
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device pci 00.0 alias gnb on end
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device pci 00.2 alias iommu off end
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device pci 01.0 alias gfx off end # internal GPU
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@ -37,8 +39,8 @@ chip soc/amd/stoneyridge
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device pci 18.5 alias ht_5 on end
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end
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device mmio 0xfedc2000 alias i2c_0 off end
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device mmio 0xfedc3000 alias i2c_1 off end
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device mmio 0xfedc4000 alias i2c_2 off end
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device mmio 0xfedc5000 alias i2c_3 off end
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device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
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end
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@ -2,8 +2,10 @@
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chip soc/amd/stoneyridge
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device cpu_cluster 0 on
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ops stoneyridge_cpu_bus_ops
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end
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device domain 0 on
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ops stoneyridge_pci_domain_ops
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device pci 00.0 alias gnb on end
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device pci 00.2 alias iommu off end
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device pci 01.0 alias gfx off end # internal GPU
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@ -31,8 +33,8 @@ chip soc/amd/stoneyridge
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device pci 18.5 alias ht_5 on end
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end
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device mmio 0xfedc2000 alias i2c_0 off end
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device mmio 0xfedc3000 alias i2c_1 off end
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device mmio 0xfedc4000 alias i2c_2 off end
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device mmio 0xfedc5000 alias i2c_3 off end
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device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
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end
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