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soc/intel/alderlake: add GPIO definitions for RPL PCH 

The RPL PCH uses a different ACPI Device ID than ADL PCH.

Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835)
Change-Id: I03f47a43ff985213ad617e834db7f974f687d877
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Tim Crawford 2023-08-11 13:21:04 -06:00 committed by Martin L Roth
parent 3ee08719ca
commit a129f8f2fe
1 changed files with 5 additions and 1 deletions
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6
src/soc/intel/alderlake/include/soc/gpio.h
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@ -3,7 +3,11 @@
#ifndef _SOC_ALDERLAKE_GPIO_H_
#define _SOC_ALDERLAKE_GPIO_H_
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#if CONFIG(SOC_INTEL_RAPTORLAKE) && CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#include <soc/gpio_defs_pch_s.h>
#define CROS_GPIO_NAME "INTC1085"
#define CROS_GPIO_DEVICE_NAME "INTC1085:00"
#elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#include <soc/gpio_defs_pch_s.h>
#define CROS_GPIO_NAME "INTC1056"
#define CROS_GPIO_DEVICE_NAME "INTC1056:00"