From a137201edd37feceb392085b30f82fce3497ff36 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 21 Apr 2021 13:52:50 -0600 Subject: [PATCH] soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities Change-Id: I97c00e1985f319ff1db57314723d8405c2a6cbd2 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/52591 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/tigerlake/gpio.c | 4 ++++ src/soc/intel/tigerlake/include/soc/pcr_ids.h | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c index 313409736e..62d57fe772 100644 --- a/src/soc/intel/tigerlake/gpio.c +++ b/src/soc/intel/tigerlake/gpio.c @@ -89,6 +89,7 @@ static const struct pad_group tgl_community5_groups[] = { static const struct pad_community tgl_communities[] = { [COMM_0] = { /* GPP B, T, A */ .port = PID_GPIOCOM0, + .cpu_port = PID_CPU_GPIOCOM0, .first_pad = GPP_B0, .last_pad = GPP_A24, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, @@ -111,6 +112,7 @@ static const struct pad_community tgl_communities[] = { }, [COMM_1] = { /* GPP S, D, H, U, VGPIO */ .port = PID_GPIOCOM1, + .cpu_port = PID_CPU_GPIOCOM1, .first_pad = GPP_S0, .last_pad = vI2S2_RXD, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, @@ -152,6 +154,7 @@ static const struct pad_community tgl_communities[] = { }, [COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */ .port = PID_GPIOCOM4, + .cpu_port = PID_CPU_GPIOCOM4, .first_pad = GPP_C0, .last_pad = GPP_DBG_PMODE, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, @@ -174,6 +177,7 @@ static const struct pad_community tgl_communities[] = { }, [COMM_5] = { /* GPP R, SPI */ .port = PID_GPIOCOM5, + .cpu_port = PID_CPU_GPIOCOM5, .first_pad = GPP_R0, .last_pad = GPP_CLK_LOOPBK, .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h index 319558aeba..03d36bf4f0 100644 --- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h +++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h @@ -31,6 +31,12 @@ #define PID_ESPI 0xc7 #define PID_SERIALIO 0xcb +/* CPU Port IDs */ +#define PID_CPU_GPIOCOM0 0xb7 +#define PID_CPU_GPIOCOM1 0xb8 +#define PID_CPU_GPIOCOM4 0xb9 +#define PID_CPU_GPIOCOM5 0xba + /* * SPI - DMI Destination ID */