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cpu/x86: Remove braces and else if unnecessary 

Fix the following warnings detected by checkpatch.pl

WARNING: braces {} are not necessary for single statement blocks
WARNING: braces {} are not necessary for any arm of this statement
WARNING: else is not generally useful after a break or return

TEST=Build and run on Galileo Gen2

Change-Id: I2d6b22c66d52f5f2d24b15270ad4b52894adebc2
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18842
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2017-03-15 14:49:35 -07:00
parent a07d0ddc44
commit a15d8af140
3 changed files with 32 additions and 53 deletions
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30
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@ -437,26 +437,22 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
/* Loop through the cpus once getting them started */
for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
if (cpu->path.type != DEVICE_PATH_APIC) {
if (cpu->path.type != DEVICE_PATH_APIC)
continue;
}
if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
continue;
if (!cpu->enabled) {
if (!cpu->enabled)
continue;
}
if (cpu->initialized) {
if (cpu->initialized)
continue;
}
if (!start_cpu(cpu)) {
if (!start_cpu(cpu))
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
udelay(10);
@ -472,9 +468,8 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
/* Loop through the cpus once to let them run through SMM relocator */
for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
if (cpu->path.type != DEVICE_PATH_APIC) {
if (cpu->path.type != DEVICE_PATH_APIC)
continue;
}
printk(BIOS_ERR, "considering CPU 0x%02x for SMM init\n",
cpu->path.apic.apic_id);
@ -482,15 +477,13 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
if (cpu == bsp_cpu)
continue;
if (!cpu->enabled) {
if (!cpu->enabled)
continue;
}
if (!start_cpu(cpu)) {
if (!start_cpu(cpu))
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
/* FIXME: endless loop */
while (atomic_read(&active_cpus) != pre_count);
@ -518,16 +511,13 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
loopcount++;
}
for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
if (cpu->path.type != DEVICE_PATH_APIC) {
if (cpu->path.type != DEVICE_PATH_APIC)
continue;
}
if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) {
if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC)
continue;
}
if (!cpu->initialized) {
if (!cpu->initialized)
printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
cpu->path.apic.apic_id);
}
}
printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount);
checkstack(_estack, 0);

47
src/cpu/x86/mp_init.c
View File

@ -140,9 +140,8 @@ static struct cpu_map cpus[CONFIG_MAX_CPUS];
static inline void barrier_wait(atomic_t *b)
{
while (atomic_read(b) == 0) {
while (atomic_read(b) == 0)
asm ("pause");
}
mfence();
}
@ -180,9 +179,8 @@ static void ap_do_flight_plan(void)
atomic_inc(&rec->cpus_entered);
barrier_wait(&rec->barrier);
if (rec->ap_call != NULL) {
if (rec->ap_call != NULL)
rec->ap_call();
}
}
}
@ -273,9 +271,8 @@ static int save_bsp_msrs(char *start, int size)
}
msr_entry = (void *)start;
for (i = 0; i < NUM_FIXED_MTRRS; i++) {
for (i = 0; i < NUM_FIXED_MTRRS; i++)
msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
}
for (i = 0; i < num_var_mtrrs; i++) {
msr_entry = save_msr(MTRR_PHYS_BASE(i), msr_entry);
@ -350,11 +347,10 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params)
/* Provide pointer to microcode patch. */
sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer;
/* Pass on abiility to load microcode in parallel. */
if (mp_params->parallel_microcode_load) {
if (mp_params->parallel_microcode_load)
sp->microcode_lock = 0;
} else {
else
sp->microcode_lock = ~0;
}
sp->c_handler = (uint32_t)&ap_init;
ap_count = &sp->ap_count;
atomic_set(ap_count, 0);
@ -386,9 +382,8 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p)
/* Assuming linear APIC space allocation. */
apic_id = info->cpu->path.apic.apic_id + i;
if (p->adjust_apic_id != NULL) {
if (p->adjust_apic_id != NULL)
apic_id = p->adjust_apic_id(i, apic_id);
}
cpu_path.apic.apic_id = apic_id;
/* Allocate the new CPU device structure */
@ -446,8 +441,8 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
printk(BIOS_DEBUG, "timed out. Aborting.\n");
return -1;
} else
printk(BIOS_DEBUG, "done.\n");
}
printk(BIOS_DEBUG, "done.\n");
}
/* Send INIT IPI to all but self. */
@ -463,8 +458,8 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
printk(BIOS_DEBUG, "timed out. Aborting.\n");
return -1;
} else
printk(BIOS_DEBUG, "done.\n");
}
printk(BIOS_DEBUG, "done.\n");
}
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
@ -474,9 +469,8 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) {
printk(BIOS_DEBUG, "timed out.\n");
return -1;
} else {
printk(BIOS_DEBUG, "done.\n");
}
printk(BIOS_DEBUG, "done.\n");
/* Wait for CPUs to check in up to 200 us. */
wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */);
@ -487,8 +481,8 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
printk(BIOS_DEBUG, "timed out. Aborting.\n");
return -1;
} else
printk(BIOS_DEBUG, "done.\n");
}
printk(BIOS_DEBUG, "done.\n");
}
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
@ -498,9 +492,8 @@ static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) {
printk(BIOS_DEBUG, "timed out.\n");
return -1;
} else {
printk(BIOS_DEBUG, "done.\n");
}
printk(BIOS_DEBUG, "done.\n");
/* Wait for CPUs to check in. */
if (wait_for_aps(num_aps, ap_count, 10000 /* 10 ms */, 50 /* us */)) {
@ -533,9 +526,8 @@ static int bsp_do_flight_plan(struct mp_params *mp_params)
}
}
if (rec->bsp_call != NULL) {
if (rec->bsp_call != NULL)
rec->bsp_call();
}
release_barrier(&rec->barrier);
}
@ -662,17 +654,16 @@ void smm_initiate_relocation_parallel(void)
if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
printk(BIOS_DEBUG, "timed out. Aborting.\n");
return;
} else
printk(BIOS_DEBUG, "done.\n");
}
printk(BIOS_DEBUG, "done.\n");
}
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid()));
lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_SMI);
if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) {
if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */))
printk(BIOS_DEBUG, "SMI Relocation timed out.\n");
} else
else
printk(BIOS_DEBUG, "Relocation complete.\n");
}
DECLARE_SPIN_LOCK(smm_relocation_lock);

8
src/cpu/x86/pae/pgtbl.c
View File

@ -72,9 +72,8 @@ void *map_2M_page(unsigned long page)
void *result;
int i;
index = cpu_index();
if (index >= CONFIG_MAX_CPUS) {
if (index >= CONFIG_MAX_CPUS)
return MAPPING_ERROR;
}
window = page >> 10;
if (window != mapped_window[index]) {
paging_off();
@ -102,10 +101,9 @@ void *map_2M_page(unsigned long page)
}
mapped_window[index] = window;
}
if (window == 0) {
if (window == 0)
result = (void *)(page << 21);
} else {
else
result = (void *)(0x80000000 | ((page & 0x3ff) << 21));
}
return result;
}