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mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device tree 

This CL selects the PcieRpClkReqDetect for the required root ports
which is needed to allow proper clksrc gpio configuration.
Also, sets the unused PcieClkSrcUsage to 0xFF.

BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe

Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Meera Ravindranath 2020-04-27 22:53:40 +05:30 committed by Patrick Georgi
parent 798fd4b69f
commit a15eaec1e6
1 changed files with 9 additions and 0 deletions
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9
src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
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@ -67,8 +67,17 @@ chip soc/intel/jasperlake
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[4]" = "1"
# Enable ClkReqDetect 1 for WLAN
# Enable ClkReqDetect 4 for NVMe
register "PcieRpClkReqDetect[1]" = "1"
register "PcieRpClkReqDetect[4]" = "1"
register "PcieClkSrcUsage[0]" = "0x04"
register "PcieClkSrcUsage[1]" = "0x01"
register "PcieClkSrcUsage[2]" = "0xFF"
register "PcieClkSrcUsage[3]" = "0xFF"
register "PcieClkSrcUsage[4]" = "0xFF"
register "PcieClkSrcUsage[5]" = "0xFF"
register "PcieClkSrcClkReq[0]" = "0x00"
register "PcieClkSrcClkReq[1]" = "0x01"