i945.h: Add some more comments, align data for better readability (trivial).
Also, add missing C1DRA2 #define (as per public datasheet). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -31,15 +31,15 @@
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#define X60BAR 0x60
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/* Northbridge BARs */
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#define DEFAULT_PCIEXBAR 0xf0000000
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#define DEFAULT_PCIEXBAR 0xf0000000 /* 4 KB per PCIe device */
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#define DEFAULT_X60BAR 0xfed13000
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#define DEFAULT_MCHBAR 0xfed14000
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#define DEFAULT_DMIBAR 0xfed18000
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#define DEFAULT_EPBAR 0xfed19000
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#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
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#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
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#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
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#define GGC 0x52
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#define GGC 0x52 /* GMCH Graphics Control */
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#define DEVEN 0x54
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_D0F0 (1 << 0)
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#define DEVEN_D1F0 (1 << 1)
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#define DEVEN_D2F0 (1 << 3)
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@ -48,22 +48,22 @@
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#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
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#endif
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#define PAM0 0x90
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#define PAM1 0x91
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#define PAM2 0x92
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#define PAM3 0x93
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#define PAM4 0x94
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#define PAM5 0x95
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#define PAM6 0x96
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#define PAM0 0x90
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#define PAM1 0x91
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#define PAM2 0x92
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#define PAM3 0x93
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#define PAM4 0x94
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#define PAM5 0x95
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#define PAM6 0x96
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#define LAC 0x97 /* Legacy Access Control */
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#define TOLUD 0x9c /* Top of Low Used Memory */
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#define SMRAM 0x9d
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#define ESMRAM 0x9e
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#define LAC 0x97 /* Legacy Access Control */
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#define TOLUD 0x9c /* Top of Low Used Memory */
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#define SMRAM 0x9d /* System Management RAM Control */
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#define ESMRAM 0x9e /* Extended System Management RAM Control */
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#define TOM 0xa0
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#define TOM 0xa0
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#define SKPAD 0xdc /* Scratchpad */
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#define SKPAD 0xdc /* Scratchpad Data */
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/* Device 0:1.0 PCI configuration space (PCI Express) */
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@ -72,7 +72,7 @@
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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#define GCFC 0xf0 /* Graphics Clock Frequency and Gating Control */
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#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */
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/*
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@ -119,6 +119,7 @@
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#define C1DRB2 0x182 /* 8bit */
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#define C1DRB3 0x183 /* 8bit */
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#define C1DRA0 0x188 /* 8bit */
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#define C1DRA2 0x189 /* 8bit */
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#define C1DCLKDIS 0x18c /* 8bit */
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#define C1BNKARC 0x18e /* 16bit */
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#define C1DRT0 0x190 /* 32bit */
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@ -152,7 +153,7 @@
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#define DQSMT 0x2f4 /* 16bit */
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#define RCVENMT 0x2f8 /* 32bit */
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#define C0R0B00DQST 0x300 /* 64bit */
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#define C0R0B00DQST 0x300 /* 64bit */
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#define C0WL0REOST 0x340 /* 8bit */
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#define C0WL1REOST 0x341 /* 8bit */
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@ -162,7 +163,7 @@
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#define C0WDLLCMC 0x36c /* 32bit */
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#define C0HCTC 0x37c /* 8bit */
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#define C1R0B00DQST 0x380 /* 64bit */
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#define C1R0B00DQST 0x380 /* 64bit */
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#define C1WL0REOST 0x3c0 /* 8bit */
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#define C1WL1REOST 0x3c1 /* 8bit */
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