GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/alderlake: add power limits for Alder Lake-N 7W soc 

Missing power limit setting for Alder-Lake-N 7W soc.
Document reference: 645548 and 646929

BUG=b:245440443
BRANCH=None
TEST=Build FW and test on nivviks board and there is no error
message "unknown SA ID: 0x4617, skipped power limits configuration."

Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Simon Yang 2022-09-06 18:30:51 +08:00 committed by Martin Roth
parent 6e007516ab
commit a16ed34638
2 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/alderlake/chip.h
View File

@ -30,6 +30,7 @@ enum soc_intel_alderlake_power_limits {
ADL_M_282_15W_CORE, ADL_M_282_15W_CORE,
ADL_M_242_CORE, ADL_M_242_CORE,
ADL_P_442_45W_CORE, ADL_P_442_45W_CORE,
ADL_N_081_7W_CORE,
ADL_N_081_15W_CORE, ADL_N_081_15W_CORE,
ADL_N_041_6W_CORE, ADL_N_041_6W_CORE,
ADL_N_021_6W_CORE, ADL_N_021_6W_CORE,
@ -57,6 +58,7 @@ enum soc_intel_alderlake_power_limits {
/* TDP values for different SKUs */ /* TDP values for different SKUs */
enum soc_intel_alderlake_cpu_tdps { enum soc_intel_alderlake_cpu_tdps {
TDP_6W = 6, TDP_6W = 6,
TDP_7W = 7,
TDP_9W = 9, TDP_9W = 9,
TDP_12W = 12, TDP_12W = 12,
TDP_15W = 15, TDP_15W = 15,
@ -90,6 +92,7 @@ static const struct {
{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W },
{ PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W },
{ PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_7W_CORE, TDP_7W },
{ PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W },
{ PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W },

6
src/soc/intel/alderlake/chipset.cb
View File

@ -48,6 +48,12 @@ chip soc/intel/alderlake
.tdp_pl4 = 68, .tdp_pl4 = 68,
}" }"
register "power_limits_config[ADL_N_081_7W_CORE]" = "{
.tdp_pl1_override = 7,
.tdp_pl2_override = 25,
.tdp_pl4 = 78,
}"
register "power_limits_config[ADL_N_081_15W_CORE]" = "{ register "power_limits_config[ADL_N_081_15W_CORE]" = "{
.tdp_pl1_override = 15, .tdp_pl1_override = 15,
.tdp_pl2_override = 35, .tdp_pl2_override = 35,