soc/intel/alderlake: Hook up FSP hyper-threading setting to option API

Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.

Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/soc/intel/alderlake/Kconfig

@@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS
 	select GENERIC_GPIO_LIB
 	select HAVE_DEBUG_RAM_SETUP
 	select HAVE_FSP_GOP
+	select HAVE_HYPERTHREADING
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE

src/soc/intel/alderlake/romstage/fsp_params.c

@@ -10,6 +10,7 @@
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pcie_rp.h>
+#include <option.h>
 #include <soc/gpio_soc_defs.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
@@ -158,8 +159,7 @@ static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
 
 	m_cfg->PrmrrSize = get_valid_prmrr_size();
 	m_cfg->EnableC6Dram = config->enable_c6dram;
-	/* Enable Hyper Threading */
-	m_cfg->HyperThreading = 1;
+	m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
 }
 
 static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg,