diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index f63d977d9e..9d4ff79c61 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -139,6 +139,16 @@ struct soc_intel_meteorlake_config {
 		SAGV_ENABLED,
 	} sagv;
 
+	/* System Agent dynamic frequency work points that memory will be training
+	 * at the enabled frequencies. Possible work points are:
+	 * 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3
+	 */
+	enum {
+		SAGV_POINTS_0_1 = 0x03,
+		SAGV_POINTS_0_1_2 = 0x07,
+		SAGV_POINTS_0_1_2_3 = 0x0f,
+	} sagv_wp_bitmap;
+
 	/* Rank Margin Tool. 1:Enable, 0:Disable */
 	uint8_t rmt;
 
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index ec5a3af4bb..38bd443b8f 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -124,6 +124,18 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_meteorlake_config *config)
 {
 	m_cfg->SaGv = config->sagv;
+	if (m_cfg->SaGv) {
+		/*
+		 * Set SaGv work points after reviewing the power and performance impact
+		 * with SaGv set to 1 (Enabled) and various work points between 0-3 being
+		 * enabled.
+		 */
+		if (config->sagv_wp_bitmap)
+			m_cfg->SaGvWpMask = config->sagv_wp_bitmap;
+		else
+			m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3;
+	}
+
 	m_cfg->RMT = config->rmt;
 	/* Enable MRC Fast Boot */
 	m_cfg->MrcFastBoot = 1;