security/memory: Clear memory in ramstage
* Add architecture independend way of clearing all DRAM * Implemented in ramstage as MTRRs need to be set to speed up clearing. Takes up to 15 seconds per GiB otherwise. * Use memset_pae on x86 * Add quirks for FSP1.0 Tested on P8H61M-Pro: * Clears 4GiB in less than 1 second Tested on wedge100s: * Clears 8GiB in 2 seconds Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 9elements Agency GmbH
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* Copyright (C) 2019 Facebook Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MEMORY_CLEAR_H
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#define MEMORY_CLEAR_H
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#include <memrange.h>
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int arch_clear_memranges(const struct memranges *mem_reserved);
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#endif /* MEMORY_CLEAR_H */
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@ -17,7 +17,9 @@ menu "Memory initialization"
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config PLATFORM_HAS_DRAM_CLEAR
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config PLATFORM_HAS_DRAM_CLEAR
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bool
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bool
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default y if ARCH_X86
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default n
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default n
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depends on RELOCATABLE_RAMSTAGE
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help
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help
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Selected by platforms that support clearing all DRAM
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Selected by platforms that support clearing all DRAM
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after DRAM initialization.
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after DRAM initialization.
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@ -1,3 +1,5 @@
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romstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
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romstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
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postcar-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
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postcar-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
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ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
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ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
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ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory_clear.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 9elements Agency GmbH
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* Copyright (C) 2019 Facebook Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#if CONFIG(ARCH_X86)
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#include <cpu/x86/pae.h>
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#else
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#define memset_pae(a, b, c, d, e) 0
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#define MEMSET_PAE_PGTL_ALIGN 0
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#define MEMSET_PAE_PGTL_SIZE 0
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#define MEMSET_PAE_PGTL_SIZE 0
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#define MEMSET_PAE_VMEM_ALIGN 0
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#endif
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#include <memrange.h>
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#include <bootmem.h>
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#include <bootstate.h>
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#include <symbols.h>
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#include <console/console.h>
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#include <arch/memory_clear.h>
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#include <string.h>
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#include <security/memory/memory.h>
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#include <cbmem.h>
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#include <arch/acpi.h>
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/* Helper to find free space for memset_pae. */
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static uintptr_t get_free_memory_range(struct memranges *mem,
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const resource_t align,
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const resource_t size)
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{
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const struct range_entry *r;
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/* Find a spot for virtual memory address */
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memranges_each_entry(r, mem) {
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if (range_entry_tag(r) != BM_MEM_RAM)
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continue;
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if (ALIGN_UP(range_entry_base(r) + size, align) + size >
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range_entry_end(r))
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continue;
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return ALIGN_UP(range_entry_base(r) + size, align);
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}
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printk(BIOS_ERR, "%s: Couldn't find free memory range\n", __func__);
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return 0;
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}
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/*
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* Clears all memory regions marked as BM_MEM_RAM.
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* Uses memset_pae if the memory region can't be accessed by memset and
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* architecture is x86.
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*
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* @return 0 on success, 1 on error
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*/
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static void clear_memory(void *unused)
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{
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const struct range_entry *r;
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struct memranges mem;
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uintptr_t pgtbl, vmem_addr;
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if (acpi_is_wakeup_s3())
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return;
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if (!security_clear_dram_request())
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return;
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/* FSP1.0 is marked as MMIO and won't appear here */
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memranges_init(&mem, IORESOURCE_MEM | IORESOURCE_FIXED |
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IORESOURCE_STORED | IORESOURCE_ASSIGNED |
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IORESOURCE_CACHEABLE,
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IORESOURCE_MEM | IORESOURCE_FIXED |
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IORESOURCE_STORED | IORESOURCE_ASSIGNED |
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IORESOURCE_CACHEABLE,
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BM_MEM_RAM);
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/* Add reserved entries */
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void *baseptr = NULL;
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size_t size = 0;
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/* Only skip CBMEM, as RELOCATABLE_RAMSTAGE is a requirement, no need
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* to separately protect stack or heap */
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cbmem_get_region(&baseptr, &size);
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memranges_insert(&mem, (uintptr_t)baseptr, size, BM_MEM_TABLE);
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if (CONFIG(PLATFORM_USES_FSP1_0)) {
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/* Protect CBMEM pointer */
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memranges_insert(&mem, CBMEM_FSP_HOB_PTR, sizeof(void *),
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BM_MEM_TABLE);
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}
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if (CONFIG(ARCH_X86)) {
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/* Find space for PAE enabled memset */
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pgtbl = get_free_memory_range(&mem, MEMSET_PAE_PGTL_ALIGN,
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MEMSET_PAE_PGTL_SIZE);
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/* Don't touch page tables while clearing */
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memranges_insert(&mem, pgtbl, MEMSET_PAE_PGTL_SIZE,
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BM_MEM_TABLE);
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vmem_addr = get_free_memory_range(&mem, MEMSET_PAE_VMEM_ALIGN,
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MEMSET_PAE_PGTL_SIZE);
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printk(BIOS_SPEW, "%s: pgtbl at %p, virt memory at %p\n",
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__func__, (void *)pgtbl, (void *)vmem_addr);
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}
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/* Now clear all useable DRAM */
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memranges_each_entry(r, &mem) {
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if (range_entry_tag(r) != BM_MEM_RAM)
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continue;
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printk(BIOS_DEBUG, "%s: Clearing DRAM %016llx-%016llx\n",
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__func__, range_entry_base(r), range_entry_end(r));
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/* Does regular memset work? */
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if (!(range_entry_end(r) >> sizeof(void *) * 8)) {
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/* fastpath */
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memset((void *)(uintptr_t)range_entry_base(r), 0,
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range_entry_size(r));
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}
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/* Use PAE if available */
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else if (CONFIG(ARCH_X86)) {
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if (memset_pae(range_entry_base(r), 0,
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range_entry_size(r), (void *)pgtbl,
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(void *)vmem_addr))
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printk(BIOS_ERR, "%s: Failed to memset "
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"memory\n", __func__);
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} else {
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printk(BIOS_ERR, "%s: Failed to memset memory\n",
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__func__);
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}
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}
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if (CONFIG(ARCH_X86)) {
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/* Clear previously skipped memory reserved for pagetables */
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printk(BIOS_DEBUG, "%s: Clearing DRAM %016lx-%016lx\n",
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__func__, pgtbl, pgtbl + MEMSET_PAE_PGTL_SIZE);
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memset((void *)pgtbl, 0, MEMSET_PAE_PGTL_SIZE);
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}
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memranges_teardown(&mem);
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}
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/* After DEV_INIT as MTRRs needs to be configured on x86 */
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, clear_memory, NULL);
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