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soc/amd/*: Move apm call out of MP init code 

This makes it easier to have common code for MP init on AMD systems.

Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2022-05-31 21:25:53 +02:00 committed by Felix Held
parent 7f611018d4
commit a19bc34430
3 changed files with 17 additions and 30 deletions
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15
src/soc/amd/cezanne/cpu.c
View File

@ -40,21 +40,12 @@ static void pre_mp_init(void)
x86_mtrr_check();
}
static void post_mp_init(void)
{
global_smi_enable();
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init,
.get_cpu_count = get_cpu_count,
.get_smm_info = get_smm_info,
.relocation_handler = smm_relocation_handler,
.post_mp_init = post_mp_init,
.post_mp_init = global_smi_enable,
};
void mp_init_cpus(struct bus *cpu_bus)
@ -65,6 +56,10 @@ void mp_init_cpus(struct bus *cpu_bus)
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static void zen_2_3_init(struct device *dev)

16
src/soc/amd/picasso/cpu.c
View File

@ -44,21 +44,12 @@ static void pre_mp_init(void)
x86_mtrr_check();
}
static void post_mp_init(void)
{
global_smi_enable();
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init,
.get_cpu_count = get_cpu_count,
.get_smm_info = get_smm_info,
.relocation_handler = smm_relocation_handler,
.post_mp_init = post_mp_init,
.post_mp_init = global_smi_enable,
};
void mp_init_cpus(struct bus *cpu_bus)
@ -69,6 +60,11 @@ void mp_init_cpus(struct bus *cpu_bus)
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static void model_17_init(struct device *dev)

16
src/soc/amd/sabrina/cpu.c
View File

@ -2,6 +2,7 @@
/* TODO: Check if this is still correct */
#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
#include <amdblocks/mca.h>
#include <amdblocks/reset.h>
@ -42,21 +43,12 @@ static void pre_mp_init(void)
x86_mtrr_check();
}
static void post_mp_init(void)
{
global_smi_enable();
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init,
.get_cpu_count = get_cpu_count,
.get_smm_info = get_smm_info,
.relocation_handler = smm_relocation_handler,
.post_mp_init = post_mp_init,
.post_mp_init = global_smi_enable,
};
void mp_init_cpus(struct bus *cpu_bus)
@ -67,6 +59,10 @@ void mp_init_cpus(struct bus *cpu_bus)
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
/* SMMINFO only needs to be set up when booting from S5 */
if (!acpi_is_wakeup_s3())
apm_control(APM_CNT_SMMINFO);
}
static void zen_2_3_init(struct device *dev)