From a19d6253f8a92ab50b279b859efce1ae27eec9d0 Mon Sep 17 00:00:00 2001
From: Felix Held <felix-coreboot@felixheld.de>
Date: Fri, 26 Nov 2021 22:47:43 +0100
Subject: [PATCH] soc/amd/stoneyridge/psp: use PSP_MAILBOX_BAR define

PSP_MAILBOX_BAR is defined as PCI_BASE_ADDRESS_4, so use it instead of
PCI_BASE_ADDRESS_4 in the code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8658b674b9adea85dfc71d7036ccf3ae17464b58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
---
 src/soc/amd/stoneyridge/psp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index 8d6290f619..b001d5f755 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -51,7 +51,7 @@ void *soc_get_mbox_address(void)
 			return 0;
 		}
 	} else {
-		psp_mmio = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) &
+		psp_mmio = pci_read_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR) &
 				~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 	}