vc/amd/fsp/picasso: add logical to lane number in port descriptor struct
The lane numbers in the PCIe/DXIO descriptor are the logical and not the physical ones, so add logical to the corresponding field names of the fsp_pcie_descriptor struct. Change-Id: I7037fed225119218e87593932815aff815e83ff8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -8,8 +8,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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{ /* MXM */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 8,
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.end_lane = 15,
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.start_logical_lane = 8,
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.end_logical_lane = 15,
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.device_number = 1,
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.function_number = 1,
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.link_aspm = ASPM_L1,
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@ -21,8 +21,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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{ /* SSD */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 0,
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.end_lane = 1,
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.start_logical_lane = 0,
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.end_logical_lane = 1,
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.device_number = 1,
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.function_number = 7,
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.link_aspm = ASPM_L1,
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@ -34,8 +34,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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{ /* WLAN */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 4,
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.end_lane = 4,
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.start_logical_lane = 4,
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.end_logical_lane = 4,
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.device_number = 1,
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.function_number = 2,
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.link_aspm = ASPM_L1,
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@ -47,8 +47,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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{ /* LAN */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 5,
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.end_lane = 5,
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.start_logical_lane = 5,
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.end_logical_lane = 5,
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.device_number = 1,
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.function_number = 3,
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.link_aspm = ASPM_L1,
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@ -60,8 +60,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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{ /* WWAN */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 6,
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.end_lane = 6,
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.start_logical_lane = 6,
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.end_logical_lane = 6,
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.device_number = 1,
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.function_number = 4,
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.link_aspm = ASPM_L1,
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@ -73,8 +73,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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{ /* WIFI */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 7,
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.end_lane = 7,
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.start_logical_lane = 7,
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.end_logical_lane = 7,
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.gpio_group_id = 1,
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.device_number = 1,
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.function_number = 5,
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@ -87,8 +87,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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{ /* SATA EXPRESS */
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.port_present = true,
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.engine_type = SATA_ENGINE,
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.start_lane = 2,
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.end_lane = 3,
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.start_logical_lane = 2,
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.end_logical_lane = 3,
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.gpio_group_id = 1,
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.channel_type = SATA_CHANNEL_LONG,
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}
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@ -98,8 +98,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
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{ /* MXM */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 8,
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.end_lane = 11,
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.start_logical_lane = 8,
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.end_logical_lane = 11,
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.device_number = 1,
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.function_number = 1,
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.link_aspm = ASPM_L1,
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@ -111,8 +111,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
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{ /* SSD */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 0,
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.end_lane = 1,
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.start_logical_lane = 0,
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.end_logical_lane = 1,
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.device_number = 1,
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.function_number = 7,
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.link_aspm = ASPM_L1,
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@ -124,8 +124,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
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{ /* WLAN */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 4,
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.end_lane = 4,
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.start_logical_lane = 4,
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.end_logical_lane = 4,
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.device_number = 1,
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.function_number = 2,
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.link_aspm = ASPM_L1,
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@ -137,8 +137,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
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{ /* LAN */
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 5,
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.end_lane = 5,
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.start_logical_lane = 5,
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.end_logical_lane = 5,
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.device_number = 1,
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.function_number = 3,
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.link_aspm = ASPM_L1,
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@ -150,8 +150,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
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{ /* SATA */
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.port_present = true,
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.engine_type = SATA_ENGINE,
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.start_lane = 2,
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.end_lane = 3,
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.start_logical_lane = 2,
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.end_logical_lane = 3,
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.gpio_group_id = 1,
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.channel_type = SATA_CHANNEL_LONG,
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}
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@ -18,8 +18,8 @@ static const fsp_pcie_descriptor pcie_descriptors[] = {
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// NVME SSD
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = NVME_START_LANE,
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.end_lane = NVME_END_LANE,
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.start_logical_lane = NVME_START_LANE,
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.end_logical_lane = NVME_END_LANE,
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.device_number = 1,
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.function_number = 7,
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.link_aspm = ASPM_L1,
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@ -33,8 +33,8 @@ static const fsp_pcie_descriptor pcie_descriptors[] = {
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// WLAN
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = WLAN_START_LANE,
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.end_lane = WLAN_END_LANE,
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.start_logical_lane = WLAN_START_LANE,
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.end_logical_lane = WLAN_END_LANE,
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.device_number = 1,
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.function_number = 2,
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.link_aspm = ASPM_L1,
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@ -48,8 +48,8 @@ static const fsp_pcie_descriptor pcie_descriptors[] = {
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// SD Reader
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = SD_START_LANE,
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.end_lane = SD_END_LANE,
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.start_logical_lane = SD_START_LANE,
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.end_logical_lane = SD_END_LANE,
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.device_number = 1,
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.function_number = 3,
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.link_aspm = ASPM_L1,
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@ -23,8 +23,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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// NVME SSD
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 0,
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.end_lane = 3,
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.start_logical_lane = 0,
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.end_logical_lane = 3,
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.device_number = 1,
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.function_number = 7,
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.link_aspm = ASPM_L1,
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@ -37,8 +37,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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// WLAN
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 4,
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.end_lane = 4,
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.start_logical_lane = 4,
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.end_logical_lane = 4,
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.device_number = 1,
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.function_number = 2,
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.link_aspm = ASPM_L1,
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@ -52,8 +52,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
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// SD Reader
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = 5,
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.end_lane = 5,
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.start_logical_lane = 5,
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.end_logical_lane = 5,
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.device_number = 1,
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.function_number = 3,
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.link_aspm = ASPM_L1,
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@ -69,8 +69,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
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// NVME SSD
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = NVME_START_LANE,
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.end_lane = NVME_END_LANE,
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.start_logical_lane = NVME_START_LANE,
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.end_logical_lane = NVME_END_LANE,
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.device_number = 1,
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.function_number = 7,
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.link_aspm = ASPM_L1,
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@ -84,8 +84,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
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// WLAN
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = WLAN_START_LANE,
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.end_lane = WLAN_END_LANE,
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.start_logical_lane = WLAN_START_LANE,
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.end_logical_lane = WLAN_END_LANE,
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.device_number = 1,
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.function_number = 2,
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.link_aspm = ASPM_L1,
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@ -99,8 +99,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
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// SD Reader
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.port_present = true,
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.engine_type = PCIE_ENGINE,
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.start_lane = SD_START_LANE,
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.end_lane = SD_END_LANE,
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.start_logical_lane = SD_START_LANE,
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.end_logical_lane = SD_END_LANE,
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.device_number = 1,
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.function_number = 3,
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.link_aspm = ASPM_L1,
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@ -113,8 +113,8 @@ typedef struct __packed {
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/* Beware that the lane numbers in here are the logical and not the physical lane numbers! */
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typedef struct __packed {
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uint8_t engine_type;
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uint8_t start_lane; // Start lane of the pci device
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uint8_t end_lane; // End lane of the pci device
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uint8_t start_logical_lane; // Start lane of the pci device
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uint8_t end_logical_lane; // End lane of the pci device
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uint8_t gpio_group_id; // FCH reset number. 0 is global reset
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uint32_t port_present :1; // Should be TRUE if train link
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uint32_t reserved_3 :7;
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