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vc/amd/fsp/picasso: add logical to lane number in port descriptor struct 

The lane numbers in the PCIe/DXIO descriptor are the logical and not the
physical ones, so add logical to the corresponding field names of the
fsp_pcie_descriptor struct.

Change-Id: I7037fed225119218e87593932815aff815e83ff8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Felix Held 2020-07-20 15:46:56 +02:00
parent a2b04f45c0
commit a19d98647b
4 changed files with 44 additions and 44 deletions
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48
src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c
View File

@ -8,8 +8,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* MXM */ { /* MXM */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 8, .start_logical_lane = 8,
.end_lane = 15, .end_logical_lane = 15,
.device_number = 1, .device_number = 1,
.function_number = 1, .function_number = 1,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -21,8 +21,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* SSD */ { /* SSD */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 0, .start_logical_lane = 0,
.end_lane = 1, .end_logical_lane = 1,
.device_number = 1, .device_number = 1,
.function_number = 7, .function_number = 7,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -34,8 +34,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* WLAN */ { /* WLAN */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 4, .start_logical_lane = 4,
.end_lane = 4, .end_logical_lane = 4,
.device_number = 1, .device_number = 1,
.function_number = 2, .function_number = 2,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -47,8 +47,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* LAN */ { /* LAN */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 5, .start_logical_lane = 5,
.end_lane = 5, .end_logical_lane = 5,
.device_number = 1, .device_number = 1,
.function_number = 3, .function_number = 3,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -60,8 +60,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* WWAN */ { /* WWAN */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 6, .start_logical_lane = 6,
.end_lane = 6, .end_logical_lane = 6,
.device_number = 1, .device_number = 1,
.function_number = 4, .function_number = 4,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -73,8 +73,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* WIFI */ { /* WIFI */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 7, .start_logical_lane = 7,
.end_lane = 7, .end_logical_lane = 7,
.gpio_group_id = 1, .gpio_group_id = 1,
.device_number = 1, .device_number = 1,
.function_number = 5, .function_number = 5,
@ -87,8 +87,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
{ /* SATA EXPRESS */ { /* SATA EXPRESS */
.port_present = true, .port_present = true,
.engine_type = SATA_ENGINE, .engine_type = SATA_ENGINE,
.start_lane = 2, .start_logical_lane = 2,
.end_lane = 3, .end_logical_lane = 3,
.gpio_group_id = 1, .gpio_group_id = 1,
.channel_type = SATA_CHANNEL_LONG, .channel_type = SATA_CHANNEL_LONG,
} }
@ -98,8 +98,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* MXM */ { /* MXM */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 8, .start_logical_lane = 8,
.end_lane = 11, .end_logical_lane = 11,
.device_number = 1, .device_number = 1,
.function_number = 1, .function_number = 1,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -111,8 +111,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* SSD */ { /* SSD */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 0, .start_logical_lane = 0,
.end_lane = 1, .end_logical_lane = 1,
.device_number = 1, .device_number = 1,
.function_number = 7, .function_number = 7,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -124,8 +124,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* WLAN */ { /* WLAN */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 4, .start_logical_lane = 4,
.end_lane = 4, .end_logical_lane = 4,
.device_number = 1, .device_number = 1,
.function_number = 2, .function_number = 2,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -137,8 +137,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* LAN */ { /* LAN */
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 5, .start_logical_lane = 5,
.end_lane = 5, .end_logical_lane = 5,
.device_number = 1, .device_number = 1,
.function_number = 3, .function_number = 3,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -150,8 +150,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
{ /* SATA */ { /* SATA */
.port_present = true, .port_present = true,
.engine_type = SATA_ENGINE, .engine_type = SATA_ENGINE,
.start_lane = 2, .start_logical_lane = 2,
.end_lane = 3, .end_logical_lane = 3,
.gpio_group_id = 1, .gpio_group_id = 1,
.channel_type = SATA_CHANNEL_LONG, .channel_type = SATA_CHANNEL_LONG,
} }

12
src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
View File

@ -18,8 +18,8 @@ static const fsp_pcie_descriptor pcie_descriptors[] = {
// NVME SSD // NVME SSD
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = NVME_START_LANE, .start_logical_lane = NVME_START_LANE,
.end_lane = NVME_END_LANE, .end_logical_lane = NVME_END_LANE,
.device_number = 1, .device_number = 1,
.function_number = 7, .function_number = 7,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -33,8 +33,8 @@ static const fsp_pcie_descriptor pcie_descriptors[] = {
// WLAN // WLAN
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = WLAN_START_LANE, .start_logical_lane = WLAN_START_LANE,
.end_lane = WLAN_END_LANE, .end_logical_lane = WLAN_END_LANE,
.device_number = 1, .device_number = 1,
.function_number = 2, .function_number = 2,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -48,8 +48,8 @@ static const fsp_pcie_descriptor pcie_descriptors[] = {
// SD Reader // SD Reader
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = SD_START_LANE, .start_logical_lane = SD_START_LANE,
.end_lane = SD_END_LANE, .end_logical_lane = SD_END_LANE,
.device_number = 1, .device_number = 1,
.function_number = 3, .function_number = 3,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,

24
src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
View File

@ -23,8 +23,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
// NVME SSD // NVME SSD
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 0, .start_logical_lane = 0,
.end_lane = 3, .end_logical_lane = 3,
.device_number = 1, .device_number = 1,
.function_number = 7, .function_number = 7,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -37,8 +37,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
// WLAN // WLAN
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 4, .start_logical_lane = 4,
.end_lane = 4, .end_logical_lane = 4,
.device_number = 1, .device_number = 1,
.function_number = 2, .function_number = 2,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -52,8 +52,8 @@ static const fsp_pcie_descriptor pco_pcie_descriptors[] = {
// SD Reader // SD Reader
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = 5, .start_logical_lane = 5,
.end_lane = 5, .end_logical_lane = 5,
.device_number = 1, .device_number = 1,
.function_number = 3, .function_number = 3,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -69,8 +69,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
// NVME SSD // NVME SSD
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = NVME_START_LANE, .start_logical_lane = NVME_START_LANE,
.end_lane = NVME_END_LANE, .end_logical_lane = NVME_END_LANE,
.device_number = 1, .device_number = 1,
.function_number = 7, .function_number = 7,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -84,8 +84,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
// WLAN // WLAN
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = WLAN_START_LANE, .start_logical_lane = WLAN_START_LANE,
.end_lane = WLAN_END_LANE, .end_logical_lane = WLAN_END_LANE,
.device_number = 1, .device_number = 1,
.function_number = 2, .function_number = 2,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
@ -99,8 +99,8 @@ static const fsp_pcie_descriptor dali_pcie_descriptors[] = {
// SD Reader // SD Reader
.port_present = true, .port_present = true,
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.start_lane = SD_START_LANE, .start_logical_lane = SD_START_LANE,
.end_lane = SD_END_LANE, .end_logical_lane = SD_END_LANE,
.device_number = 1, .device_number = 1,
.function_number = 3, .function_number = 3,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,

4
src/vendorcode/amd/fsp/picasso/platform_descriptors.h
View File

@ -113,8 +113,8 @@ typedef struct __packed {
/* Beware that the lane numbers in here are the logical and not the physical lane numbers! */ /* Beware that the lane numbers in here are the logical and not the physical lane numbers! */
typedef struct __packed { typedef struct __packed {
uint8_t engine_type; uint8_t engine_type;
uint8_t start_lane; // Start lane of the pci device uint8_t start_logical_lane; // Start lane of the pci device
uint8_t end_lane; // End lane of the pci device uint8_t end_logical_lane; // End lane of the pci device
uint8_t gpio_group_id; // FCH reset number. 0 is global reset uint8_t gpio_group_id; // FCH reset number. 0 is global reset
uint32_t port_present :1; // Should be TRUE if train link uint32_t port_present :1; // Should be TRUE if train link
uint32_t reserved_3 :7; uint32_t reserved_3 :7;