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mb/google/brya/var/gimble: disabled autonomous GPIO power management 

Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:200918380
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I83cc1a5d80bf23d052e83c9791ef866966a3d9b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58626
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mark Hsieh 2021-10-26 22:15:25 +08:00 committed by Felix Held
parent 3d1fff9c01
commit a1b299cd69
1 changed files with 10 additions and 0 deletions
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10
src/mainboard/google/brya/variants/gimble/overridetree.cb
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@ -21,6 +21,16 @@ fw_config
end
end
chip soc/intel/alderlake
# This disabled autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses; need to clarify
# the minimum PCH IRQ pulse width with Intel, b/180111628
register "gpio_override_pm" = "1"
register "gpio_pm[COMM_0]" = "0"
register "gpio_pm[COMM_1]" = "0"
register "gpio_pm[COMM_2]" = "0"
register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0"
register "SaGv" = "SaGv_Enabled"
register "TcssAuxOri" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"