intel/skylake: Fix issues found by klockwork
src/soc/intel/skylake/acpi.c Function cbmem_find may return NULL, check before using its result. src/soc/intel/skylake/flash_controller.c Remove dead code: spi_claim_bus is a no-op, always returning 0. src/soc/intel/skylake/gpio.c Check for NULL before using pointers. src/soc/intel/skylake/igd.c Don't copy 0-termination of signature string. src/soc/intel/skylake/lpc.c Don't check unsigned >= 0. src/soc/intel/skylake/systemagent.c Explicitly cast result to 64bit. BRANCH=None BUG=chrome-os-partner:48542 TEST=Built & booted Kunimitsu board. Change-Id: I6cbf4f78382383d3c8c3b15f66c5898ab5bf183a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d98a8cdd3d095a6943c0e104cd4938639a62bd14 Original-Change-Id: Id2a31402618f4c9f6f53525ebcf6b71fd67428db Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317522 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12991 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
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@ -573,11 +573,15 @@ void southcluster_inject_dsdt(device_t device)
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/* Save wake source information for calculating ACPI _SWS values */
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int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
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{
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struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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struct chipset_power_state *ps;
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static uint32_t gpe0_sts[GPE0_REG_MAX];
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uint32_t pm1_en;
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int i;
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ps = cbmem_find(CBMEM_ID_POWER_STATE);
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if (ps == NULL)
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return -1;
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/* PM1_EN state is lost in Deep S3 so enable basic wake events */
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pm1_en = ps->pm1_en | PCIEXPWAK_STS | RTC_STS | PWRBTN_STS | BM_STS;
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*pm1 = ps->pm1_sts & pm1_en;
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@ -191,11 +191,6 @@ int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len)
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}
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flash->spi->rw = SPI_WRITE_FLAG;
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ret = spi_claim_bus(flash->spi);
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if (ret) {
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printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
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return ret;
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}
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start = offset;
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end = start + len;
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@ -261,6 +261,9 @@ static void gpio_handle_pad_mode(const struct pad_config *cfg)
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bit = 0;
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hostsw_own_reg = gpio_hostsw_reg(cfg->pad, &bit);
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if (hostsw_own_reg == NULL)
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return;
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reg = read32(hostsw_own_reg);
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reg &= ~(1U << bit);
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@ -282,7 +285,8 @@ static void gpi_enable_smi(gpio_t pad)
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uint32_t pad_mask;
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comm = gpio_get_community(pad);
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if (comm == NULL)
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return;
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regs = pcr_port_regs(comm->port_id);
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gpi_status_reg = (void *)®s[GPI_SMI_STS_OFFSET];
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gpi_en_reg = (void *)®s[GPI_SMI_EN_OFFSET];
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@ -118,7 +118,7 @@ static int init_igd_opregion(igd_opregion_t *opregion)
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die("vbt data not found");
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memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
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sizeof(IGD_OPREGION_SIGNATURE));
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sizeof(IGD_OPREGION_SIGNATURE) - 1);
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
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sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
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@ -209,9 +209,12 @@ static inline int pch_io_range_in_default(u16 base, u16 size)
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if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
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return 0;
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/* Is it entirely contained? */
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if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
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(base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
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/*
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* Is it entirely contained?
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* Since LPC_DEFAULT_IO_RANGE_LOWER is Zero,
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* it need not be checked against lower base.
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*/
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if ((base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
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return 1;
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/* This will return not in range for partial overlaps. */
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@ -183,7 +183,7 @@ static void read_map_entry(device_t dev, struct map_entry *entry,
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value <<= 32;
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}
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value |= pci_read_config32(dev, entry->reg);
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value |= (uint64_t) pci_read_config32(dev, entry->reg);
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value &= mask;
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if (entry->is_limit)
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