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mb/google/nissa: Add fmd file for nissa 

Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash
layout for brya is of 32MB size, and nissa is expected to have 16MB SPI
NOR flash. The current composition of AP firmware exceeds 16MB. To get
an estimate of the unutilized region in the current flash layout for
nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware
size to under 16MB and to remove the RW_UNUSED regions from the final
fmd file.

Below table gives the size reduction from brya fmd to nissa fmd:

+----------------+-------------------+---------------+
|     Region     | Earlier size (KB) | New size (KB) |
+================+===================+===============+
|      SI_ME     |        5116       |      3772     |
+----------------+-------------------+---------------+
| RW_SECTION_A/B |        8192       |      4344     |
+----------------+-------------------+---------------+
|   VBLOCK_A/B   |         64        |       8       |
+----------------+-------------------+---------------+
|    ME_RW_A/B*  |        3008       |      1434     |
+----------------+-------------------+---------------+
|    RW_LEGACY   |        2048       |      1024     |
+----------------+-------------------+---------------+
|     RW_ELOG    |         16        |       4       |
+----------------+-------------------+---------------+
|   SHARED_DATA  |         8         |       4       |
+----------------+-------------------+---------------+
|   VBLOCK_DEV   |         8         |       0       |
+----------------+-------------------+---------------+
|  RW_SPD_CACHE  |         4         |       0       |
+----------------+-------------------+---------------+
|    RW_NVRAM    |         24        |       8       |
+----------------+-------------------+---------------+
|      WP_RO     |        8192       |      4096     |
+----------------+-------------------+---------------+
|       GBB      |        448        |       12      |
+----------------+-------------------+---------------+

*Based on LZMA compression on ME_RW_A/B regions. With LZMA compression,
this region can be 1434K. Without this, ~665K will be more in each of
these regions.
Patch: https://review.coreboot.org/c/coreboot/+/62358/

BUG=b:202783191
BRANCH=None
TEST=Build and boot Nivviks.

Cq-Depend: chrome-internal:4584911
Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
This commit is contained in:
Krishna Prasad Bhat 2022-02-25 16:07:21 +05:30 committed by Felix Held
parent dddcdc5f73
commit a1b9f9f611
2 changed files with 59 additions and 0 deletions
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1
src/mainboard/google/brya/Kconfig
View File

@ -125,6 +125,7 @@ config DRIVER_TPM_I2C_ADDR
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_KANO || BOARD_GOOGLE_BRASK
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
config TPM_TIS_ACPI_INTERRUPT

58
src/mainboard/google/brya/chromeos-nissa.fmd Normal file
View File

@ -0,0 +1,58 @@
FLASH 32M {
SI_ALL 3776K {
SI_DESC 4K
SI_ME {
CSE_LAYOUT 8K
CSE_RO 1360K
CSE_DATA 420K
# 64-KiB aligned to optimize RW erases during CSE update.
CSE_RW 1984K
}
}
SI_BIOS 28992K {
RW_SECTION_A 4344K {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 64
ME_RW_A(CBFS) 1434K
}
RW_LEGACY(CBFS) 1M
RW_MISC 152K {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
RW_MRC_CACHE 64K
}
RW_ELOG(PRESERVE) 4K
RW_SHARED 4K {
SHARED_DATA 4K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 8K
}
# RW UNUSED Region 1.
RW_UNUSED_1 7088K
# This section starts at the 16M boundary in SPI flash.
# ADL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 4344K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
ME_RW_B(CBFS) 1434K
}
# RW UNUSED Region 2.
RW_UNUSED_2 7944K
# Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO 4M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 12K
COREBOOT(CBFS)
}
}
}
}