soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver
This change uses the newly added meminit block driver and updates ADL SoC and mainboard code accordingly. BUG=b:172978729 Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Furquan Shaikh
parent
13d6a4647d
commit
a1c247b55d
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@ -6,6 +6,14 @@
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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static const struct mb_cfg ddr4_mem_config = {
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static const struct mb_cfg ddr4_mem_config = {
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.type = MEM_TYPE_DDR4,
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.ect = true, /* Early Command Training */
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.UserBd = BOARD_TYPE_MOBILE,
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.ddr_config = {
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/* Baseboard uses only 100ohm Rcomp resistors */
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/* Baseboard uses only 100ohm Rcomp resistors */
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.rcomp_resistor = {100, 100, 100},
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.rcomp_resistor = {100, 100, 100},
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@ -13,66 +21,133 @@ static const struct mb_cfg ddr4_mem_config = {
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.rcomp_targets = {40, 30, 33, 33, 30},
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.rcomp_targets = {40, 30, 33, 33, 30},
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.dq_pins_interleaved = false,
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.dq_pins_interleaved = false,
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},
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.ect = true, /* Early Command Training */
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.UserBd = BOARD_TYPE_MOBILE,
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};
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};
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static const struct mb_cfg lpddr4_mem_config = {
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static const struct mb_cfg lpddr4_mem_config = {
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.type = MEM_TYPE_LP4X,
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/* DQ byte map */
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/* DQ byte map */
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.dq_map = {
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.lpx_dq_map = {
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{ 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15 },
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.ddr0 = {
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{ 12, 8, 14, 10, 11, 13, 15, 9, 5, 0, 7, 3, 6, 2, 1, 4 },
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.dq0 = { 0, 2, 3, 1, 6, 7, 5, 4, },
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{ 3, 0, 2, 1, 6, 5, 4, 7, 12, 13, 14, 15, 10, 9, 8, 11 },
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.dq1 = { 10, 8, 11, 9, 14, 12, 13, 15, },
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{ 2, 6, 7, 1, 3, 4, 0, 5, 9, 13, 8, 15, 14, 11, 12, 10 },
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},
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{ 3, 0, 1, 2, 7, 4, 6, 5, 10, 8, 11, 9, 14, 13, 12, 15 },
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.ddr1 = {
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{ 10, 12, 14, 8, 9, 13, 15, 11, 3, 7, 6, 2, 0, 4, 5, 1 },
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.dq0 = { 12, 8, 14, 10, 11, 13, 15, 9, },
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{ 12, 15, 14, 13, 9, 10, 11, 8, 7, 4, 6, 5, 0, 1, 3, 2 },
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.dq1 = { 5, 0, 7, 3, 6, 2, 1, 4, },
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{ 0, 2, 4, 3, 1, 6, 7, 5, 13, 9, 10, 11, 8, 12, 14, 15 },
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},
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.ddr2 = {
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.dq0 = { 3, 0, 2, 1, 6, 5, 4, 7, },
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.dq1 = { 12, 13, 14, 15, 10, 9, 8, 11, },
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},
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.ddr3 = {
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.dq0 = { 2, 6, 7, 1, 3, 4, 0, 5, },
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.dq1 = { 9, 13, 8, 15, 14, 11, 12, 10, },
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},
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.ddr4 = {
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.dq0 = { 3, 0, 1, 2, 7, 4, 6, 5, },
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.dq1 = { 10, 8, 11, 9, 14, 13, 12, 15, },
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},
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.ddr5 = {
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.dq0 = { 10, 12, 14, 8, 9, 13, 15, 11, },
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.dq1 = { 3, 7, 6, 2, 0, 4, 5, 1, },
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},
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.ddr6 = {
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.dq0 = { 12, 15, 14, 13, 9, 10, 11, 8, },
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.dq1 = { 7, 4, 6, 5, 0, 1, 3, 2, },
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},
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.ddr7 = {
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.dq0 = { 0, 2, 4, 3, 1, 6, 7, 5, },
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.dq1 = { 13, 9, 10, 11, 8, 12, 14, 15, },
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},
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},
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},
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/* DQS CPU<>DRAM map */
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/* DQS CPU<>DRAM map */
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.dqs_map = {
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.lpx_dqs_map = {
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{ 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 }
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.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
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.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
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.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
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.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
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},
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},
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.dq_pins_interleaved = false,
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.ect = true, /* Early Command Training */
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.ect = true, /* Early Command Training */
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.UserBd = BOARD_TYPE_MOBILE,
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.UserBd = BOARD_TYPE_MOBILE,
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};
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};
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static const struct mb_cfg lp5_mem_config = {
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static const struct mb_cfg lp5_mem_config = {
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.type = MEM_TYPE_LP5X,
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/* DQ byte map */
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/* DQ byte map */
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.dq_map = {
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.lpx_dq_map = {
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{ 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 },
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.ddr0 = {
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{ 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 },
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.dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, },
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{ 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 },
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.dq1 = { 15, 14, 12, 13, 8, 9, 10, 11, },
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{ 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 },
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},
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{ 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 },
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.ddr1 = {
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{ 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 },
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.dq0 = { 0, 2, 3, 1, 5, 7, 4, 6, },
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{ 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 },
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.dq1 = { 14, 13, 15, 12, 8, 9, 11, 10, },
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{ 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 },
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},
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.ddr2 = {
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.dq0 = { 1, 2, 0, 3, 4, 6, 5, 7, },
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.dq1 = { 15, 13, 12, 14, 9, 10, 8, 11, },
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},
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.ddr3 = {
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.dq0 = { 2, 1, 3, 0, 7, 4, 5, 6, },
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.dq1 = { 13, 12, 15, 14, 9, 11, 8, 10, },
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},
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.ddr4 = {
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.dq0 = { 1, 2, 3, 0, 6, 4, 5, 7, },
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.dq1 = { 15, 13, 14, 12, 10, 9, 8, 11, },
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},
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.ddr5 = {
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.dq0 = { 1, 0, 3, 2, 6, 7, 4, 5, },
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.dq1 = { 14, 12, 15, 13, 8, 9, 10, 11, },
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},
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.ddr6 = {
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.dq0 = { 0, 2, 1, 3, 4, 7, 5, 6, },
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.dq1 = { 12, 13, 15, 14, 9, 11, 10, 8, },
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},
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.ddr7 = {
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.dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, },
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.dq1 = { 13, 15, 11, 12, 10, 9, 14, 8, },
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},
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},
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},
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/* DQS CPU<>DRAM map */
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/* DQS CPU<>DRAM map */
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.dqs_map = {
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.lpx_dqs_map = {
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{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
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.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
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},
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},
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.dq_pins_interleaved = false,
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.ect = false, /* Early Command Training */
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.ect = false, /* Early Command Training */
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.lp5_ccc_config = 0xff,
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.UserBd = BOARD_TYPE_MOBILE,
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.UserBd = BOARD_TYPE_MOBILE,
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.lp5x_config = {
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.ccc_config = 0xff,
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},
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};
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};
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static const struct mb_cfg ddr5_mem_config = {
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static const struct mb_cfg ddr5_mem_config = {
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.type = MEM_TYPE_DDR5,
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.ect = true, /* Early Command Training */
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.UserBd = BOARD_TYPE_MOBILE,
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.ddr_config = {
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/* Baseboard uses only 100ohm Rcomp resistors */
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/* Baseboard uses only 100ohm Rcomp resistors */
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.rcomp_resistor = {100, 100, 100},
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.rcomp_resistor = {100, 100, 100},
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@ -80,10 +155,7 @@ static const struct mb_cfg ddr5_mem_config = {
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.rcomp_targets = {50, 30, 30, 30, 27},
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.rcomp_targets = {50, 30, 30, 30, 27},
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.dq_pins_interleaved = false,
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.dq_pins_interleaved = false,
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}
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.ect = true, /* Early Command Training */
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.UserBd = BOARD_TYPE_MOBILE,
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};
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};
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const struct mb_cfg *variant_memory_params(void)
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const struct mb_cfg *variant_memory_params(void)
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@ -31,19 +31,21 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
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int board_id = get_board_id();
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int board_id = get_board_id();
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const bool half_populated = false;
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const bool half_populated = false;
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const struct spd_info lp4_lp5_spd_info = {
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const struct mem_spd lp4_lp5_spd_info = {
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.read_type = READ_SPD_CBFS,
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.topo = MEM_TOPO_MEMORY_DOWN,
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.spd_spec.spd_index = get_spd_index(),
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.cbfs_index = get_spd_index(),
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};
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};
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const struct spd_info ddr4_ddr5_spd_info = {
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const struct mem_spd ddr4_ddr5_spd_info = {
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.read_type = READ_SMBUS,
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.topo = MEM_TOPO_DIMM_MODULE,
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.spd_spec = {
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.smbus = {
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.spd_smbus_address = {
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[0] = {
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[0] = 0xa0,
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.addr_dimm[0] = 0xa0,
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[1] = 0xa2,
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.addr_dimm[1] = 0xa2,
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[8] = 0xa4,
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},
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[9] = 0xa6,
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[1] = {
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.addr_dimm[0] = 0xa4,
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.addr_dimm[1] = 0xa6,
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},
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},
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},
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},
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};
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};
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@ -55,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
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select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_MEMINIT
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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@ -250,4 +251,17 @@ config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
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0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
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0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
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3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
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3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
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6:Enable (2-wire DCI OOB), 7:Manual
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6:Enable (2-wire DCI OOB), 7:Manual
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config DATA_BUS_WIDTH
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int
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default 128
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config DIMMS_PER_CHANNEL
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int
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default 2
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config MRC_CHANNEL_WIDTH
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int
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default 16
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endif
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endif
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@ -5,106 +5,102 @@
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#include <stddef.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdint.h>
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#include <types.h>
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#include <fsp/soc_binding.h>
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#include <fsp/soc_binding.h>
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#include <intelblocks/meminit.h>
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#define BYTES_PER_CHANNEL 2
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enum mem_type {
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#define BITS_PER_BYTE 8
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MEM_TYPE_DDR4,
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#define DQS_PER_CHANNEL 2
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MEM_TYPE_DDR5,
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MEM_TYPE_LP4X,
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/* 64-bit Channel identification */
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MEM_TYPE_LP5X,
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enum {
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DDR_CH0,
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DDR_CH1,
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DDR_CH2,
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DDR_CH3,
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DDR_CH4,
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DDR_CH5,
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DDR_CH6,
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DDR_CH7,
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DDR_NUM_CHANNELS
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};
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/* Number of memory DIMM slots available on Alderlake board */
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#define NUM_DIMM_SLOT 16
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struct spd_by_pointer {
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size_t spd_data_len;
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uintptr_t spd_data_ptr;
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};
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};
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enum mem_info_read_type {
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struct mem_ddr_config {
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NOT_EXISTING, /* No memory in this slot */
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/* Dqs Pins Interleaved Setting. Enable/Disable Control */
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READ_SMBUS, /* Read on-module spd by SMBUS. */
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bool dq_pins_interleaved;
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READ_SPD_CBFS, /* Find SPD file in CBFS. */
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READ_SPD_MEMPTR /* Find SPD data from pointer. */
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};
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struct spd_info {
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enum mem_info_read_type read_type;
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union spd_data_by {
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/* To read on-module SPD when read_type is READ_SMBUS. */
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uint8_t spd_smbus_address[NUM_DIMM_SLOT];
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/* To identify SPD file when read_type is READ_SPD_CBFS. */
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int spd_index;
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/* To find SPD data when read_type is READ_SPD_MEMPTR. */
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struct spd_by_pointer spd_data_ptr_info;
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} spd_spec;
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};
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/* Board-specific memory configuration information */
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struct mb_cfg {
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/* DQ mapping */
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uint8_t dq_map[DDR_NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE];
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/*
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* DQS CPU<>DRAM map. Each array entry represents a
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* mapping of a dq bit on the CPU to the bit it's connected to on
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* the memory part. The array index represents the dqs bit number
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* on the memory part, and the values in the array represent which
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* pin on the CPU that DRAM pin connects to.
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*/
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uint8_t dqs_map[DDR_NUM_CHANNELS][DQS_PER_CHANNEL];
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||||||
|
|
||||||
/*
|
/*
|
||||||
* Rcomp resistor values. These values represent the resistance in
|
* Rcomp resistor values. These values represent the resistance in
|
||||||
* ohms of the three rcomp resistors attached to the DDR_COMP_0,
|
* ohms of the three rcomp resistors attached to the DDR_COMP_0,
|
||||||
* DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
|
* DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
|
||||||
*/
|
*/
|
||||||
uint16_t rcomp_resistor[3];
|
uint16_t rcomp_resistor[3];
|
||||||
|
|
||||||
/* Rcomp target values. */
|
/* Rcomp target values. */
|
||||||
uint16_t rcomp_targets[5];
|
uint16_t rcomp_targets[5];
|
||||||
|
};
|
||||||
|
|
||||||
/*
|
struct lpx_dq {
|
||||||
* Dqs Pins Interleaved Setting. Enable/Disable Control
|
uint8_t dq0[BITS_PER_BYTE];
|
||||||
* TRUE = enable, FALSE = disable
|
uint8_t dq1[BITS_PER_BYTE];
|
||||||
*/
|
};
|
||||||
bool dq_pins_interleaved;
|
|
||||||
|
|
||||||
|
struct lpx_dqs {
|
||||||
|
uint8_t dqs0;
|
||||||
|
uint8_t dqs1;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct lpx_dq_map {
|
||||||
|
struct lpx_dq ddr0;
|
||||||
|
struct lpx_dq ddr1;
|
||||||
|
struct lpx_dq ddr2;
|
||||||
|
struct lpx_dq ddr3;
|
||||||
|
struct lpx_dq ddr4;
|
||||||
|
struct lpx_dq ddr5;
|
||||||
|
struct lpx_dq ddr6;
|
||||||
|
struct lpx_dq ddr7;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct lpx_dqs_map {
|
||||||
|
struct lpx_dqs ddr0;
|
||||||
|
struct lpx_dqs ddr1;
|
||||||
|
struct lpx_dqs ddr2;
|
||||||
|
struct lpx_dqs ddr3;
|
||||||
|
struct lpx_dqs ddr4;
|
||||||
|
struct lpx_dqs ddr5;
|
||||||
|
struct lpx_dqs ddr6;
|
||||||
|
struct lpx_dqs ddr7;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mem_lp5x_config {
|
||||||
|
uint8_t ccc_config;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mb_cfg {
|
||||||
|
enum mem_type type;
|
||||||
|
|
||||||
|
union {
|
||||||
/*
|
/*
|
||||||
* Early Command Training Enable/Disable Control
|
* DQ CPU<>DRAM map:
|
||||||
* TRUE = enable, FALSE = disable
|
* Index of the array represents DQ# on the CPU and the value represents DQ# on
|
||||||
|
* the DRAM part.
|
||||||
*/
|
*/
|
||||||
|
uint8_t dq_map[CONFIG_DATA_BUS_WIDTH];
|
||||||
|
struct lpx_dq_map lpx_dq_map;
|
||||||
|
};
|
||||||
|
|
||||||
|
union {
|
||||||
|
/*
|
||||||
|
* DQS CPU<>DRAM map:
|
||||||
|
* Index of the array represents DQS# on the CPU and the value represents DQS#
|
||||||
|
* on the DRAM part.
|
||||||
|
*/
|
||||||
|
uint8_t dqs_map[CONFIG_DATA_BUS_WIDTH/BITS_PER_BYTE];
|
||||||
|
struct lpx_dqs_map lpx_dqs_map;
|
||||||
|
};
|
||||||
|
|
||||||
|
union {
|
||||||
|
struct mem_lp5x_config lp5x_config;
|
||||||
|
struct mem_ddr_config ddr_config;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Early Command Training Enable/Disable Control */
|
||||||
bool ect;
|
bool ect;
|
||||||
|
|
||||||
/* Board type */
|
/* Board type */
|
||||||
uint8_t UserBd;
|
uint8_t UserBd;
|
||||||
|
|
||||||
/*
|
|
||||||
* Command pins mapping for Controller Channel (ccc)
|
|
||||||
* lp5_ccc_config: Bitmask where bits [3:0] are Controller 0 Channel [3:0] and
|
|
||||||
* bits [7:4] are Controller 1 Channel [3:0]
|
|
||||||
* Bit value: 0 = ccc pin mapping is ascending, 1 = ccc pin mapping is descending.
|
|
||||||
*/
|
|
||||||
uint8_t lp5_ccc_config;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
|
||||||
* Initialize default memory configurations for Alder Lake.
|
const struct mem_spd *spd_info, bool half_populated);
|
||||||
*/
|
|
||||||
|
|
||||||
void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
|
|
||||||
const struct spd_info *spd_info, bool half_populated);
|
|
||||||
|
|
||||||
#endif /* _SOC_ALDERLAKE_MEMINIT_H_ */
|
#endif /* _SOC_ALDERLAKE_MEMINIT_H_ */
|
||||||
|
|
|
||||||
|
|
@ -1,185 +1,240 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||||
|
|
||||||
#include <assert.h>
|
|
||||||
#include <console/console.h>
|
#include <console/console.h>
|
||||||
#include <fsp/util.h>
|
#include <fsp/util.h>
|
||||||
#include <soc/meminit.h>
|
#include <soc/meminit.h>
|
||||||
#include <spd_bin.h>
|
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
|
|
||||||
enum dimm_enable_options {
|
#define LPX_PHYSICAL_CH_WIDTH 16
|
||||||
ENABLE_BOTH_DIMMS = 0,
|
#define LPX_CHANNELS CHANNEL_COUNT(LPX_PHYSICAL_CH_WIDTH)
|
||||||
DISABLE_DIMM0 = 1,
|
|
||||||
DISABLE_DIMM1 = 2,
|
#define DDR4_PHYSICAL_CH_WIDTH 64
|
||||||
DISABLE_BOTH_DIMMS = 3
|
#define DDR4_CHANNELS CHANNEL_COUNT(DDR4_PHYSICAL_CH_WIDTH)
|
||||||
|
|
||||||
|
#define DDR5_PHYSICAL_CH_WIDTH 32
|
||||||
|
#define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
|
||||||
|
|
||||||
|
static void meminit_lp4x(FSP_M_CONFIG *mem_cfg)
|
||||||
|
{
|
||||||
|
mem_cfg->DqPinsInterleaved = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void meminit_lp5x(FSP_M_CONFIG *mem_cfg, const struct mem_lp5x_config *lp5x_config)
|
||||||
|
{
|
||||||
|
mem_cfg->DqPinsInterleaved = 0;
|
||||||
|
mem_cfg->Lp5CccConfig = lp5x_config->ccc_config;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct mem_ddr_config *ddr_config)
|
||||||
|
{
|
||||||
|
mem_cfg->DqPinsInterleaved = ddr_config->dq_pins_interleaved;
|
||||||
|
memcpy(&mem_cfg->RcompResistor, ddr_config->rcomp_resistor,
|
||||||
|
sizeof(mem_cfg->RcompResistor));
|
||||||
|
memcpy(&mem_cfg->RcompTarget, ddr_config->rcomp_targets, sizeof(mem_cfg->RcompTarget));
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct soc_mem_cfg soc_mem_cfg[] = {
|
||||||
|
[MEM_TYPE_DDR4] = {
|
||||||
|
.num_phys_channels = DDR4_CHANNELS,
|
||||||
|
.phys_to_mrc_map = {
|
||||||
|
[0] = 0,
|
||||||
|
[1] = 4,
|
||||||
|
},
|
||||||
|
.md_phy_masks = {
|
||||||
|
/*
|
||||||
|
* Only physical channel 0 is populated in case of half-populated
|
||||||
|
* configuration.
|
||||||
|
*/
|
||||||
|
.half_channel = BIT(0),
|
||||||
|
/* In mixed topologies, channel 1 is always memory-down. */
|
||||||
|
.mixed_topo = BIT(1),
|
||||||
|
},
|
||||||
|
},
|
||||||
|
[MEM_TYPE_DDR5] = {
|
||||||
|
.num_phys_channels = DDR5_CHANNELS,
|
||||||
|
.phys_to_mrc_map = {
|
||||||
|
[0] = 0,
|
||||||
|
[1] = 1,
|
||||||
|
[2] = 4,
|
||||||
|
[3] = 5,
|
||||||
|
},
|
||||||
|
.md_phy_masks = {
|
||||||
|
/*
|
||||||
|
* Physical channels 0 and 1 are populated in case of
|
||||||
|
* half-populated configurations.
|
||||||
|
*/
|
||||||
|
.half_channel = BIT(0) | BIT(1),
|
||||||
|
/* In mixed topologies, channels 2 and 3 are always memory-down. */
|
||||||
|
.mixed_topo = BIT(2) | BIT(3),
|
||||||
|
},
|
||||||
|
},
|
||||||
|
[MEM_TYPE_LP4X] = {
|
||||||
|
.num_phys_channels = LPX_CHANNELS,
|
||||||
|
.phys_to_mrc_map = {
|
||||||
|
[0] = 0,
|
||||||
|
[1] = 1,
|
||||||
|
[2] = 2,
|
||||||
|
[3] = 3,
|
||||||
|
[4] = 4,
|
||||||
|
[5] = 5,
|
||||||
|
[6] = 6,
|
||||||
|
[7] = 7,
|
||||||
|
},
|
||||||
|
.md_phy_masks = {
|
||||||
|
/*
|
||||||
|
* Physical channels 0, 1, 2 and 3 are populated in case of
|
||||||
|
* half-populated configurations.
|
||||||
|
*/
|
||||||
|
.half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3),
|
||||||
|
/* LP4x does not support mixed topologies. */
|
||||||
|
},
|
||||||
|
},
|
||||||
|
[MEM_TYPE_LP5X] = {
|
||||||
|
.num_phys_channels = LPX_CHANNELS,
|
||||||
|
.phys_to_mrc_map = {
|
||||||
|
[0] = 0,
|
||||||
|
[1] = 1,
|
||||||
|
[2] = 2,
|
||||||
|
[3] = 3,
|
||||||
|
[4] = 4,
|
||||||
|
[5] = 5,
|
||||||
|
[6] = 6,
|
||||||
|
[7] = 7,
|
||||||
|
},
|
||||||
|
.md_phy_masks = {
|
||||||
|
/*
|
||||||
|
* Physical channels 0, 1, 2 and 3 are populated in case of
|
||||||
|
* half-populated configurations.
|
||||||
|
*/
|
||||||
|
.half_channel = BIT(0) | BIT(1) | BIT(2) | BIT(3),
|
||||||
|
/* LP5x does not support mixed topologies. */
|
||||||
|
},
|
||||||
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static void spd_read_from_cbfs(const struct spd_info *spd_info,
|
static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
|
||||||
uintptr_t *spd_data_ptr, size_t *spd_data_len)
|
|
||||||
{
|
{
|
||||||
struct region_device spd_rdev;
|
uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
|
||||||
size_t spd_index = spd_info->spd_spec.spd_index;
|
[0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, },
|
||||||
|
[1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, },
|
||||||
|
[2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, },
|
||||||
|
[3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, },
|
||||||
|
[4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, },
|
||||||
|
[5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, },
|
||||||
|
[6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, },
|
||||||
|
[7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, },
|
||||||
|
};
|
||||||
|
uint8_t *disable_dimm_upds[MRC_CHANNELS] = {
|
||||||
|
&mem_cfg->DisableDimmMc0Ch0,
|
||||||
|
&mem_cfg->DisableDimmMc0Ch1,
|
||||||
|
&mem_cfg->DisableDimmMc0Ch2,
|
||||||
|
&mem_cfg->DisableDimmMc0Ch3,
|
||||||
|
&mem_cfg->DisableDimmMc1Ch0,
|
||||||
|
&mem_cfg->DisableDimmMc1Ch1,
|
||||||
|
&mem_cfg->DisableDimmMc1Ch2,
|
||||||
|
&mem_cfg->DisableDimmMc1Ch3,
|
||||||
|
};
|
||||||
|
size_t ch, dimm;
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index);
|
mem_cfg->MemorySpdDataLen = data->spd_len;
|
||||||
if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
|
|
||||||
die("spd.bin not found or incorrect index\n");
|
|
||||||
|
|
||||||
*spd_data_len = region_device_sz(&spd_rdev);
|
for (ch = 0; ch < MRC_CHANNELS; ch++) {
|
||||||
|
uint8_t *disable_dimm_ptr = disable_dimm_upds[ch];
|
||||||
|
*disable_dimm_ptr = 0;
|
||||||
|
|
||||||
/* Memory leak is ok since we have memory mapped boot media */
|
for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
|
||||||
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
|
uint32_t *spd_ptr = spd_upds[ch][dimm];
|
||||||
|
|
||||||
*spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
|
*spd_ptr = data->spd[ch][dimm];
|
||||||
|
if (!*spd_ptr)
|
||||||
|
*disable_dimm_ptr |= BIT(dimm);
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void get_spd_data(const struct spd_info *spd_info,
|
static void mem_init_dq_dqs_upds(void *upds[MRC_CHANNELS], const void *map, size_t upd_size,
|
||||||
uintptr_t *spd_data_ptr, size_t *spd_data_len)
|
const struct mem_channel_data *data, bool auto_detect)
|
||||||
{
|
{
|
||||||
if (spd_info->read_type == READ_SPD_MEMPTR) {
|
size_t i;
|
||||||
*spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr;
|
|
||||||
*spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len;
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (spd_info->read_type == READ_SPD_CBFS) {
|
for (i = 0; i < MRC_CHANNELS; i++, map += upd_size) {
|
||||||
spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len);
|
if (auto_detect ||
|
||||||
return;
|
!channel_is_populated(i, MRC_CHANNELS, data->ch_population_flags))
|
||||||
|
memset(upds[i], 0, upd_size);
|
||||||
|
else
|
||||||
|
memcpy(upds[i], map, upd_size);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg,
|
static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
|
||||||
const struct mb_cfg *board_cfg,
|
const struct mb_cfg *mb_cfg, bool auto_detect)
|
||||||
bool half_populated)
|
|
||||||
{
|
{
|
||||||
memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor,
|
void *dq_upds[MRC_CHANNELS] = {
|
||||||
sizeof(mem_cfg->RcompResistor));
|
&mem_cfg->DqMapCpu2DramCh0,
|
||||||
|
&mem_cfg->DqMapCpu2DramCh1,
|
||||||
|
&mem_cfg->DqMapCpu2DramCh2,
|
||||||
|
&mem_cfg->DqMapCpu2DramCh3,
|
||||||
|
&mem_cfg->DqMapCpu2DramCh4,
|
||||||
|
&mem_cfg->DqMapCpu2DramCh5,
|
||||||
|
&mem_cfg->DqMapCpu2DramCh6,
|
||||||
|
&mem_cfg->DqMapCpu2DramCh7,
|
||||||
|
};
|
||||||
|
|
||||||
memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets,
|
const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0);
|
||||||
sizeof(mem_cfg->RcompTarget));
|
|
||||||
|
|
||||||
memcpy(&mem_cfg->DqMapCpu2DramCh0, &board_cfg->dq_map[DDR_CH0],
|
_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!");
|
||||||
sizeof(board_cfg->dq_map[DDR_CH0]));
|
|
||||||
memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0],
|
|
||||||
sizeof(board_cfg->dqs_map[DDR_CH0]));
|
|
||||||
|
|
||||||
memcpy(&mem_cfg->DqMapCpu2DramCh1, &board_cfg->dq_map[DDR_CH1],
|
mem_init_dq_dqs_upds(dq_upds, mb_cfg->dq_map, upd_size, data, auto_detect);
|
||||||
sizeof(board_cfg->dq_map[DDR_CH1]));
|
|
||||||
memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1],
|
|
||||||
sizeof(board_cfg->dqs_map[DDR_CH1]));
|
|
||||||
|
|
||||||
memcpy(&mem_cfg->DqMapCpu2DramCh2, &board_cfg->dq_map[DDR_CH2],
|
|
||||||
sizeof(board_cfg->dq_map[DDR_CH2]));
|
|
||||||
memcpy(&mem_cfg->DqsMapCpu2DramCh2, &board_cfg->dqs_map[DDR_CH2],
|
|
||||||
sizeof(board_cfg->dqs_map[DDR_CH2]));
|
|
||||||
|
|
||||||
memcpy(&mem_cfg->DqMapCpu2DramCh3, &board_cfg->dq_map[DDR_CH3],
|
|
||||||
sizeof(board_cfg->dq_map[DDR_CH3]));
|
|
||||||
memcpy(&mem_cfg->DqsMapCpu2DramCh3, &board_cfg->dqs_map[DDR_CH3],
|
|
||||||
sizeof(board_cfg->dqs_map[DDR_CH3]));
|
|
||||||
|
|
||||||
if (half_populated)
|
|
||||||
return;
|
|
||||||
|
|
||||||
memcpy(&mem_cfg->DqMapCpu2DramCh4, &board_cfg->dq_map[DDR_CH4],
|
|
||||||
sizeof(board_cfg->dq_map[DDR_CH4]));
|
|
||||||
memcpy(&mem_cfg->DqsMapCpu2DramCh4, &board_cfg->dqs_map[DDR_CH4],
|
|
||||||
sizeof(board_cfg->dqs_map[DDR_CH4]));
|
|
||||||
|
|
||||||
memcpy(&mem_cfg->DqMapCpu2DramCh5, &board_cfg->dq_map[DDR_CH5],
|
|
||||||
sizeof(board_cfg->dq_map[DDR_CH5]));
|
|
||||||
memcpy(&mem_cfg->DqsMapCpu2DramCh5, &board_cfg->dqs_map[DDR_CH5],
|
|
||||||
sizeof(board_cfg->dqs_map[DDR_CH5]));
|
|
||||||
|
|
||||||
memcpy(&mem_cfg->DqMapCpu2DramCh6, &board_cfg->dq_map[DDR_CH6],
|
|
||||||
sizeof(board_cfg->dq_map[DDR_CH6]));
|
|
||||||
memcpy(&mem_cfg->DqsMapCpu2DramCh6, &board_cfg->dqs_map[DDR_CH6],
|
|
||||||
sizeof(board_cfg->dqs_map[DDR_CH6]));
|
|
||||||
|
|
||||||
memcpy(&mem_cfg->DqMapCpu2DramCh7, &board_cfg->dq_map[DDR_CH7],
|
|
||||||
sizeof(board_cfg->dq_map[DDR_CH7]));
|
|
||||||
memcpy(&mem_cfg->DqsMapCpu2DramCh7, &board_cfg->dqs_map[DDR_CH7],
|
|
||||||
sizeof(board_cfg->dqs_map[DDR_CH7]));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void meminit_channels(FSP_M_CONFIG *mem_cfg,
|
static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
|
||||||
const struct mb_cfg *board_cfg,
|
const struct mb_cfg *mb_cfg, bool auto_detect)
|
||||||
uintptr_t spd_data_ptr,
|
|
||||||
bool half_populated)
|
|
||||||
{
|
{
|
||||||
uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */
|
void *dqs_upds[MRC_CHANNELS] = {
|
||||||
|
&mem_cfg->DqsMapCpu2DramCh0,
|
||||||
|
&mem_cfg->DqsMapCpu2DramCh1,
|
||||||
|
&mem_cfg->DqsMapCpu2DramCh2,
|
||||||
|
&mem_cfg->DqsMapCpu2DramCh3,
|
||||||
|
&mem_cfg->DqsMapCpu2DramCh4,
|
||||||
|
&mem_cfg->DqsMapCpu2DramCh5,
|
||||||
|
&mem_cfg->DqsMapCpu2DramCh6,
|
||||||
|
&mem_cfg->DqsMapCpu2DramCh7,
|
||||||
|
};
|
||||||
|
|
||||||
/* Channel 0 */
|
const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0);
|
||||||
mem_cfg->DisableDimmMc0Ch0 = dimm_cfg;
|
|
||||||
mem_cfg->MemorySpdPtr00 = spd_data_ptr;
|
|
||||||
mem_cfg->MemorySpdPtr01 = 0;
|
|
||||||
|
|
||||||
/* Channel 1 */
|
_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!");
|
||||||
mem_cfg->DisableDimmMc0Ch1 = dimm_cfg;
|
|
||||||
mem_cfg->MemorySpdPtr02 = spd_data_ptr;
|
|
||||||
mem_cfg->MemorySpdPtr03 = 0;
|
|
||||||
|
|
||||||
/* Channel 2 */
|
mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect);
|
||||||
mem_cfg->DisableDimmMc0Ch2 = dimm_cfg;
|
|
||||||
mem_cfg->MemorySpdPtr04 = spd_data_ptr;
|
|
||||||
mem_cfg->MemorySpdPtr05 = 0;
|
|
||||||
|
|
||||||
/* Channel 3 */
|
|
||||||
mem_cfg->DisableDimmMc0Ch3 = dimm_cfg;
|
|
||||||
mem_cfg->MemorySpdPtr06 = spd_data_ptr;
|
|
||||||
mem_cfg->MemorySpdPtr07 = 0;
|
|
||||||
|
|
||||||
if (half_populated) {
|
|
||||||
printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__);
|
|
||||||
dimm_cfg = DISABLE_BOTH_DIMMS;
|
|
||||||
spd_data_ptr = 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Channel 4 */
|
void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg,
|
||||||
mem_cfg->DisableDimmMc1Ch0 = dimm_cfg;
|
const struct mem_spd *spd_info, bool half_populated)
|
||||||
mem_cfg->MemorySpdPtr08 = spd_data_ptr;
|
|
||||||
mem_cfg->MemorySpdPtr09 = 0;
|
|
||||||
|
|
||||||
/* Channel 5 */
|
|
||||||
mem_cfg->DisableDimmMc1Ch1 = dimm_cfg;
|
|
||||||
mem_cfg->MemorySpdPtr10 = spd_data_ptr;
|
|
||||||
mem_cfg->MemorySpdPtr11 = 0;
|
|
||||||
|
|
||||||
/* Channel 6 */
|
|
||||||
mem_cfg->DisableDimmMc1Ch2 = dimm_cfg;
|
|
||||||
mem_cfg->MemorySpdPtr12 = spd_data_ptr;
|
|
||||||
mem_cfg->MemorySpdPtr13 = 0;
|
|
||||||
|
|
||||||
/* Channel 7 */
|
|
||||||
mem_cfg->DisableDimmMc1Ch3 = dimm_cfg;
|
|
||||||
mem_cfg->MemorySpdPtr14 = spd_data_ptr;
|
|
||||||
mem_cfg->MemorySpdPtr15 = 0;
|
|
||||||
|
|
||||||
meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Initialize onboard memory configurations for lpddr4x */
|
|
||||||
void memcfg_init(FSP_M_CONFIG *mem_cfg,
|
|
||||||
const struct mb_cfg *board_cfg,
|
|
||||||
const struct spd_info *spd_info,
|
|
||||||
bool half_populated)
|
|
||||||
{
|
{
|
||||||
if (spd_info->read_type == READ_SMBUS) {
|
struct mem_channel_data data;
|
||||||
for (int i = 0; i < NUM_DIMM_SLOT; i++)
|
bool dq_dqs_auto_detect = false;
|
||||||
mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i];
|
|
||||||
meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
|
|
||||||
} else {
|
|
||||||
size_t spd_data_len = 0;
|
|
||||||
uintptr_t spd_data_ptr = 0;
|
|
||||||
|
|
||||||
memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable));
|
mem_cfg->ECT = mb_cfg->ect;
|
||||||
get_spd_data(spd_info, &spd_data_ptr, &spd_data_len);
|
mem_cfg->UserBd = mb_cfg->UserBd;
|
||||||
|
|
||||||
mem_cfg->MemorySpdDataLen = spd_data_len;
|
switch (mb_cfg->type) {
|
||||||
meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated);
|
case MEM_TYPE_DDR4:
|
||||||
|
case MEM_TYPE_DDR5:
|
||||||
|
meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
|
||||||
|
dq_dqs_auto_detect = true;
|
||||||
|
break;
|
||||||
|
case MEM_TYPE_LP4X:
|
||||||
|
meminit_lp4x(mem_cfg);
|
||||||
|
break;
|
||||||
|
case MEM_TYPE_LP5X:
|
||||||
|
meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
die("Unsupported memory type(%d)\n", mb_cfg->type);
|
||||||
}
|
}
|
||||||
|
|
||||||
mem_cfg->Lp5CccConfig = board_cfg->lp5_ccc_config;
|
mem_populate_channel_data(&soc_mem_cfg[mb_cfg->type], spd_info, half_populated, &data);
|
||||||
mem_cfg->ECT = board_cfg->ect;
|
mem_init_spd_upds(mem_cfg, &data);
|
||||||
mem_cfg->UserBd = board_cfg->UserBd;
|
mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
|
||||||
mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved;
|
mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue