skylake: Use common ACPI _SWS code

Enable and use the common code for filling out the NVS data used
by the _SWS methods.  Add a function to provide the wake source
data.  With Deep S3 enabled skylake does not retain the contents
of the PM1_EN register so instead just select the wake related
events in PM1_STS.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=tested on glados by checking for valid _SWS string in
/sys/firmware/log after suspend/resume.  Wake sources that were
tested are RTC, power button, keypress, trackpad, and wifi.

Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0
Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298169
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11648
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Duncan Laurie 2015-09-08 16:12:44 -07:00 committed by Patrick Georgi
parent 47a0b8494b
commit a1c8b34d7b
3 changed files with 25 additions and 18 deletions

View File

@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_MODULES select RELOCATABLE_MODULES
select RELOCATABLE_RAMSTAGE select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_FSP_RAM_INIT select SOC_INTEL_COMMON_FSP_RAM_INIT
select SOC_INTEL_COMMON_FSP_ROMSTAGE select SOC_INTEL_COMMON_FSP_ROMSTAGE
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET

View File

@ -37,6 +37,7 @@
#include <cpu/intel/turbo.h> #include <cpu/intel/turbo.h>
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h> #include <vendorcode/google/chromeos/gnvs.h>
#include <soc/intel/common/acpi.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/cpu.h> #include <soc/cpu.h>
#include <soc/iomap.h> #include <soc/iomap.h>
@ -604,6 +605,26 @@ void southcluster_inject_dsdt(device_t device)
} }
} }
/* Save wake source information for calculating ACPI _SWS values */
int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
{
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
static uint32_t gpe0_sts[GPE0_REG_MAX];
uint32_t pm1_en;
int i;
/* PM1_EN state is lost in Deep S3 so enable basic wake events */
pm1_en = ps->pm1_en | PCIEXPWAK_STS | RTC_STS | PWRBTN_STS | BM_STS;
*pm1 = ps->pm1_sts & pm1_en;
/* Mask off GPE0 status bits that are not enabled */
*gpe0 = &gpe0_sts[0];
for (i = 0; i < GPE0_REG_MAX; i++)
gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
return GPE0_REG_MAX;
}
__attribute__((weak)) void acpi_mainboard_gnvs(global_nvs_t *gnvs) __attribute__((weak)) void acpi_mainboard_gnvs(global_nvs_t *gnvs)
{ {
} }

View File

@ -19,6 +19,9 @@
* Foundation, Inc. * Foundation, Inc.
*/ */
/* Enable ACPI _SWS methods */
#include <soc/intel/common/acpi/acpi_wake_source.asl>
/* The APM port can be used for generating software SMIs */ /* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2) OperationRegion (APMP, SystemIO, 0xb2, 2)
@ -83,21 +86,3 @@ Method (_WAK, 1)
{ {
Return (Package (){ 0, 0 }) Return (Package (){ 0, 0 })
} }
Scope (\_SB)
{
Method (_SWS)
{
/* Index into PM1 for device that caused wake */
Return (\PM1I)
}
}
Scope (\_GPE)
{
Method (_SWS)
{
/* Index into GPE for device that caused wake */
Return (\GPEI)
}
}