skylake: Use common ACPI _SWS code
Enable and use the common code for filling out the NVS data used by the _SWS methods. Add a function to provide the wake source data. With Deep S3 enabled skylake does not retain the contents of the PM1_EN register so instead just select the wake related events in PM1_STS. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados by checking for valid _SWS string in /sys/firmware/log after suspend/resume. Wake sources that were tested are RTC, power button, keypress, trackpad, and wifi. Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0 Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298169 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11648 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
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select RELOCATABLE_MODULES
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select RELOCATABLE_RAMSTAGE
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_FSP_RAM_INIT
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select SOC_INTEL_COMMON_FSP_ROMSTAGE
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select SOC_INTEL_COMMON_RESET
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@ -37,6 +37,7 @@
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#include <cpu/intel/turbo.h>
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#include <ec/google/chromeec/ec.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <soc/intel/common/acpi.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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@ -604,6 +605,26 @@ void southcluster_inject_dsdt(device_t device)
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}
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}
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/* Save wake source information for calculating ACPI _SWS values */
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int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
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{
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struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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static uint32_t gpe0_sts[GPE0_REG_MAX];
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uint32_t pm1_en;
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int i;
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/* PM1_EN state is lost in Deep S3 so enable basic wake events */
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pm1_en = ps->pm1_en | PCIEXPWAK_STS | RTC_STS | PWRBTN_STS | BM_STS;
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*pm1 = ps->pm1_sts & pm1_en;
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/* Mask off GPE0 status bits that are not enabled */
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*gpe0 = &gpe0_sts[0];
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for (i = 0; i < GPE0_REG_MAX; i++)
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gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i];
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return GPE0_REG_MAX;
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}
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__attribute__((weak)) void acpi_mainboard_gnvs(global_nvs_t *gnvs)
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{
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}
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@ -19,6 +19,9 @@
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* Foundation, Inc.
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*/
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/* Enable ACPI _SWS methods */
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#include <soc/intel/common/acpi/acpi_wake_source.asl>
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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@ -83,21 +86,3 @@ Method (_WAK, 1)
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{
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Return (Package (){ 0, 0 })
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}
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Scope (\_SB)
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{
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Method (_SWS)
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{
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/* Index into PM1 for device that caused wake */
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Return (\PM1I)
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}
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}
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Scope (\_GPE)
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{
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Method (_SWS)
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{
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/* Index into GPE for device that caused wake */
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Return (\GPEI)
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}
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}
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