* ICH7 SPI support
* fix some variable names in ichspi.c (Offset -> offset) * Dump ICH7 SPI bar with -V * Improve error message in case IOPL goes wrong. (It might not even be an IOPL) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
20e0599e69
commit
a1dd9142c6
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@ -189,15 +189,16 @@ void *ich_spibar = NULL;
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static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar)
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{
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uint8_t old, new, bbs;
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uint8_t old, new, bbs, buc;
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uint32_t tmp, gcs;
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void *rcrb;
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/* Read the Root Complex Base Address Register (RCBA) */
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tmp = pci_read_long(dev, 0xf0);
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/* Calculate the Root Complex Register Block address */
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tmp &= 0xffffc000;
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printf_debug("Root Complex Register Block address = 0x%x\n", tmp);
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printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
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rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp);
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if (rcrb == MAP_FAILED) {
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perror("Can't mmap memory using " MEM_DEV);
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@ -212,11 +213,42 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsign
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printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs,
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(bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
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buc = *(volatile uint8_t *)(rcrb + 0x3414);
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printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled");
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/* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
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printf_debug("SPIBAR = 0x%lx\n", tmp + spibar);
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/* TODO: Dump the SPI config regs */
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printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, (uint16_t)spibar);
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// Assign Virtual Address
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ich_spibar = rcrb + spibar;
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if (ich7_detected) {
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int i;
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printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(ich_spibar + 0));
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printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(ich_spibar + 2));
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printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(ich_spibar + 4));
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for (i=0; i < 8; i++) {
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int offs;
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offs = 8 + (i * 8);
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printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
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printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(ich_spibar + offs +4), i);
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}
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printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(ich_spibar + 0x50));
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printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(ich_spibar + 0x54));
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printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(ich_spibar + 0x56));
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printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(ich_spibar + 0x58));
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printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(ich_spibar + 0x5c));
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for (i=0; i < 4; i++) {
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int offs;
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offs = 0x60 + (i * 4);
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printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
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}
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printf_debug("\n");
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if ( (*(uint16_t *)ich_spibar) & (1 << 15)) {
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printf("WARNING: SPI Configuration Lockdown activated.\n");
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}
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}
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old = pci_read_byte(dev, 0xdc);
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printf_debug("SPI Read Configuration: ");
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new = (old >> 2) & 0x3;
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@ -234,11 +266,16 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsign
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return enable_flash_ich_dc(dev, name);
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}
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/* Flag for ICH7 SPI register block */
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int ich7_detected = 0;
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static int enable_flash_ich7(struct pci_dev *dev, const char *name)
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{
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ich7_detected = 1;
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return enable_flash_ich_dc_spi(dev, name, 0x3020);
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}
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/* Flag for ICH8/ICH9 SPI register block */
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int ich9_detected = 0;
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static int enable_flash_ich8(struct pci_dev *dev, const char *name)
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@ -370,6 +370,7 @@ void print_supported_boards(void);
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/* chipset_enable.c */
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int chipset_flash_enable(void);
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void print_supported_chipsets(void);
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extern int ich7_detected;
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extern int ich9_detected;
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extern void *ich_spibar;
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@ -378,7 +378,7 @@ int main(int argc, char *argv[])
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#else
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if (iopl(3) != 0) {
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#endif
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fprintf(stderr, "ERROR: iopl failed: \"%s\"\n",
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fprintf(stderr, "ERROR: Could not get IO privileges (%s).\nYou need to be root.\n",
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strerror(errno));
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exit(1);
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}
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@ -4,6 +4,7 @@
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* Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
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* Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
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* Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
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* Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -42,15 +43,17 @@
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#define MAXDATABYTES 0x40
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/*ICH9 controller register definition*/
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#define REG_FADDR 0x08 /* 32 Bits */
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#define REG_FDATA0 0x10 /* 64 Bytes */
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#define REG_SSFS 0x90 /* 08 Bits */
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/* ICH9 controller register definition */
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#define ICH9_REG_FADDR 0x08 /* 32 Bits */
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#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
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#define ICH9_REG_SSFS 0x90 /* 08 Bits */
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#define SSFS_SCIP 0x00000001
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#define SSFS_CDS 0x00000004
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#define SSFS_FCERR 0x00000008
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#define SSFS_AEL 0x00000010
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#define REG_SSFC 0x91 /* 24 Bits */
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#define ICH9_REG_SSFC 0x91 /* 24 Bits */
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#define SSFC_SCGO 0x00000200
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#define SSFC_ACS 0x00000400
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#define SSFC_SPOP 0x00000800
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@ -61,9 +64,10 @@
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#define SSFC_SCF 0x01000000
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#define SSFC_SCF_20MHZ 0x00000000
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#define SSFC_SCF_33MHZ 0x01000000
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#define REG_PREOP 0x94 /* 16 Bits */
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#define REG_OPTYPE 0x96 /* 16 Bits */
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#define REG_OPMENU 0x98 /* 64 BITS */
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#define ICH9_REG_PREOP 0x94 /* 16 Bits */
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#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
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#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
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// ICH9R SPI commands
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#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
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@ -71,6 +75,24 @@
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#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
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#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
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// ICH7 registers
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#define ICH7_REG_SPIS 0x00 /* 16 Bits */
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#define SPIS_SCIP 0x00000001
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#define SPIS_CDS 0x00000004
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#define SPIS_FCERR 0x00000008
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#define ICH7_REG_SPIC 0x02 /* 16 Bits */
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#define SPIC_SCGO 0x0002
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#define SPIC_ACS 0x0004
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#define SPIC_SPOP 0x0008
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#define SPIC_DS 0x4000
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#define ICH7_REG_SPIA 0x04 /* 32 Bits */
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#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
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#define ICH7_REG_PREOP 0x54 /* 16 Bits */
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#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
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#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
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typedef struct _OPCODE {
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uint8_t opcode; //This commands spi opcode
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uint8_t spi_type; //This commands spi type
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@ -101,7 +123,14 @@ static OPCODES *curopcodes = NULL;
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static inline uint32_t REGREAD32(int X)
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{
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volatile uint32_t regval;
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regval = *(volatile uint32_t *)((uint8_t *) ich_spibar + X);
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regval = *(volatile uint32_t *) ((uint8_t *) ich_spibar + X);
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return regval;
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}
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static inline uint16_t REGREAD16(int X)
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{
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volatile uint16_t regval;
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regval = *(volatile uint16_t *) ((uint8_t *) ich_spibar + X);
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return regval;
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}
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@ -114,9 +143,9 @@ static int program_opcodes(OPCODES * op);
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static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
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uint8_t datalength, uint8_t * data);
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static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
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int Offset);
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int offset);
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static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
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int Offset);
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int offset);
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static int ich_spi_erase_block(struct flashchip *flash, int offset);
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OPCODES O_ST_M25P = {
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@ -147,37 +176,61 @@ int program_opcodes(OPCODES * op)
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temp16 = (op->preop[0]);
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/* 8:16 Prefix Opcode 2 */
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temp16 |= ((uint16_t) op->preop[1]) << 8;
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REGWRITE16(REG_PREOP, temp16);
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if (ich7_detected) {
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REGWRITE16(ICH7_REG_PREOP, temp16);
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} else if (ich9_detected) {
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REGWRITE16(ICH9_REG_PREOP, temp16);
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}
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/*Program Opcode Types 0 - 7 */
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/* Program Opcode Types 0 - 7 */
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temp16 = 0;
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for (a = 0; a < 8; a++) {
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temp16 |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
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}
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REGWRITE16(REG_OPTYPE, temp16);
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/*Program Allowable Opcodes 0 - 3 */
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if (ich7_detected) {
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REGWRITE16(ICH7_REG_OPTYPE, temp16);
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} else if (ich9_detected) {
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REGWRITE16(ICH9_REG_OPTYPE, temp16);
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}
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/* Program Allowable Opcodes 0 - 3 */
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temp32 = 0;
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for (a = 0; a < 4; a++) {
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temp32 |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
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}
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REGWRITE32(REG_OPMENU, temp32);
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if (ich7_detected) {
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REGWRITE32(ICH7_REG_OPMENU, temp32);
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} else if (ich9_detected) {
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REGWRITE32(ICH9_REG_OPMENU, temp32);
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}
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/*Program Allowable Opcodes 4 - 7 */
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temp32 = 0;
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for (a = 4; a < 8; a++) {
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temp32 |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
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temp32 |=
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((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
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}
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if (ich7_detected) {
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REGWRITE32(ICH7_REG_OPMENU + 4, temp32);
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} else if (ich9_detected) {
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REGWRITE32(ICH9_REG_OPMENU + 4, temp32);
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}
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REGWRITE32(REG_OPMENU + 4, temp32);
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return 0;
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}
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int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength,
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uint8_t * data)
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static int ich7_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
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uint8_t datalength, uint8_t * data)
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{
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int write_cmd = 0;
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int timeout;
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uint32_t temp32;
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uint16_t temp16;
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uint32_t a;
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/* Is it a write command? */
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@ -187,7 +240,7 @@ int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength,
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}
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/* Programm Offset in Flash into FADDR */
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REGWRITE32(REG_FADDR, (offset & 0x00FFFFFF)); /*SPI addresses are 24 BIT only */
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REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
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/* Program data into FDATA0 to N */
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if (write_cmd && (datalength != 0)) {
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@ -200,12 +253,115 @@ int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength,
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temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
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if ((a % 4) == 3) {
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REGWRITE32(REG_FDATA0 + (a - (a % 4)), temp32);
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REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
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temp32);
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}
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}
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if (((a - 1) % 4) != 3) {
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REGWRITE32(REG_FDATA0 + ((a - 1) - ((a - 1) % 4)),
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temp32);
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REGWRITE32(ICH7_REG_SPID0 +
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((a - 1) - ((a - 1) % 4)), temp32);
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}
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}
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/* Assemble SPIS */
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temp16 = 0;
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/* clear error status registers */
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temp16 |= (SPIS_CDS + SPIS_FCERR);
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REGWRITE16(ICH7_REG_SPIS, temp16);
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/* Assemble SPIC */
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temp16 = 0;
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if (datalength != 0) {
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temp16 |= SPIC_DS;
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temp16 |= ((uint16_t) ((datalength - 1) & 0x3f)) << 8;
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}
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/* Select opcode */
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temp16 |= ((uint16_t) (nr & 0x07)) << 4;
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/* Handle Atomic */
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if (op.atomic != 0) {
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/* Select atomic command */
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temp16 |= SPIC_ACS;
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/* Selct prefix opcode */
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if ((op.atomic - 1) == 1) {
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/*Select prefix opcode 2 */
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temp16 |= SPIC_SPOP;
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}
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}
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/* Start */
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temp16 |= SPIC_SCGO;
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/* write it */
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REGWRITE16(ICH7_REG_SPIC, temp16);
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/* wait for cycle complete */
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timeout = 1000 * 60; // 60s is a looong timeout.
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while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
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myusec_delay(1000);
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}
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if (!timeout) {
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printf_debug("timeout\n");
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}
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if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
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printf_debug("Transaction error!\n");
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return 1;
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}
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if ((!write_cmd) && (datalength != 0)) {
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for (a = 0; a < datalength; a++) {
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if ((a % 4) == 0) {
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temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
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}
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data[a] =
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(temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
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>> ((a % 4) * 8);
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}
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}
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return 0;
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}
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static int ich9_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
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uint8_t datalength, uint8_t * data)
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{
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int write_cmd = 0;
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uint32_t temp32;
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uint32_t a;
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/* Is it a write command? */
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if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
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|| (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
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write_cmd = 1;
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}
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/* Programm Offset in Flash into FADDR */
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REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
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/* Program data into FDATA0 to N */
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if (write_cmd && (datalength != 0)) {
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temp32 = 0;
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for (a = 0; a < datalength; a++) {
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if ((a % 4) == 0) {
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temp32 = 0;
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}
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temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
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if ((a % 4) == 3) {
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REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
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temp32);
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}
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}
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if (((a - 1) % 4) != 3) {
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REGWRITE32(ICH9_REG_FDATA0 +
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((a - 1) - ((a - 1) % 4)), temp32);
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}
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}
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@ -243,15 +399,15 @@ int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength,
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temp32 |= SSFC_SCGO;
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/* write it */
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REGWRITE32(REG_SSFS, temp32);
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REGWRITE32(ICH9_REG_SSFS, temp32);
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/*wait for cycle complete */
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while ((REGREAD32(REG_SSFS) & SSFS_CDS) == 0) {
|
||||
while ((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) {
|
||||
/*TODO; Do something that this can't lead into an endless loop. but some
|
||||
* commands may cause this to be last more than 30 seconds */
|
||||
}
|
||||
|
||||
if ((REGREAD32(REG_SSFS) & SSFS_FCERR) != 0) {
|
||||
if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
|
||||
printf_debug("Transaction error!\n");
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -259,21 +415,35 @@ int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength,
|
|||
if ((!write_cmd) && (datalength != 0)) {
|
||||
for (a = 0; a < datalength; a++) {
|
||||
if ((a % 4) == 0) {
|
||||
temp32 = REGREAD32(REG_FDATA0 + (a));
|
||||
temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
|
||||
}
|
||||
|
||||
data[a] =
|
||||
(temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) >>
|
||||
((a % 4) * 8);
|
||||
(temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
|
||||
>> ((a % 4) * 8);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
|
||||
uint8_t datalength, uint8_t * data)
|
||||
{
|
||||
if (ich7_detected)
|
||||
return ich7_run_opcode(nr, op, offset, datalength, data);
|
||||
else if (ich9_detected) {
|
||||
return ich9_run_opcode(nr, op, offset, datalength, data);
|
||||
}
|
||||
|
||||
/* If we ever get here, something really weird happened */
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int ich_spi_erase_block(struct flashchip *flash, int offset)
|
||||
{
|
||||
printf_debug("Spi_Erase,Offset=%d,sectors=%d\n", offset, 1);
|
||||
printf_debug("ich_spi_erase_block: offset=%d, sectors=%d\n",
|
||||
offset, 1);
|
||||
|
||||
if (run_opcode(2, curopcodes->opcode[2], offset, 0, NULL) != 0) {
|
||||
printf_debug("Error erasing sector at 0x%x", offset);
|
||||
|
|
@ -285,21 +455,21 @@ static int ich_spi_erase_block(struct flashchip *flash, int offset)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int Offset)
|
||||
static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset)
|
||||
{
|
||||
int page_size = flash->page_size;
|
||||
uint32_t remaining = flash->page_size;
|
||||
int a;
|
||||
|
||||
printf_debug("Spi_Read,Offset=%d,number=%d,buf=%p\n", Offset, page_size,
|
||||
buf);
|
||||
printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n",
|
||||
offset, page_size, buf);
|
||||
|
||||
for (a = 0; a < page_size; a += MAXDATABYTES) {
|
||||
if (remaining < MAXDATABYTES) {
|
||||
|
||||
if (run_opcode
|
||||
(1, curopcodes->opcode[1],
|
||||
Offset + (page_size - remaining), remaining,
|
||||
offset + (page_size - remaining), remaining,
|
||||
&buf[page_size - remaining]) != 0) {
|
||||
printf_debug("Error reading");
|
||||
return 1;
|
||||
|
|
@ -308,7 +478,7 @@ static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int Offset)
|
|||
} else {
|
||||
if (run_opcode
|
||||
(1, curopcodes->opcode[1],
|
||||
Offset + (page_size - remaining), MAXDATABYTES,
|
||||
offset + (page_size - remaining), MAXDATABYTES,
|
||||
&buf[page_size - remaining]) != 0) {
|
||||
printf_debug("Error reading");
|
||||
return 1;
|
||||
|
|
@ -321,20 +491,20 @@ static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int Offset)
|
|||
}
|
||||
|
||||
static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
|
||||
int Offset)
|
||||
int offset)
|
||||
{
|
||||
int page_size = flash->page_size;
|
||||
uint32_t remaining = page_size;
|
||||
int a;
|
||||
|
||||
printf_debug("write_page_ichspi,Offset=%d,number=%d,buf=%p\n", Offset,
|
||||
page_size, bytes);
|
||||
printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
|
||||
offset, page_size, bytes);
|
||||
|
||||
for (a = 0; a < page_size; a += MAXDATABYTES) {
|
||||
if (remaining < MAXDATABYTES) {
|
||||
if (run_opcode
|
||||
(0, curopcodes->opcode[0],
|
||||
Offset + (page_size - remaining), remaining,
|
||||
offset + (page_size - remaining), remaining,
|
||||
&bytes[page_size - remaining]) != 0) {
|
||||
printf_debug("Error writing");
|
||||
return 1;
|
||||
|
|
@ -343,7 +513,7 @@ static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
|
|||
} else {
|
||||
if (run_opcode
|
||||
(0, curopcodes->opcode[0],
|
||||
Offset + (page_size - remaining), MAXDATABYTES,
|
||||
offset + (page_size - remaining), MAXDATABYTES,
|
||||
&bytes[page_size - remaining]) != 0) {
|
||||
printf_debug("Error writing");
|
||||
return 1;
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the flashrom project.
|
||||
*
|
||||
* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
|
||||
* Copyright (C) 2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -35,6 +36,8 @@ int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char
|
|||
{
|
||||
if (it8716f_flashport)
|
||||
return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
|
||||
else if (ich7_detected)
|
||||
return ich_spi_command(writecnt, readcnt, writearr, readarr);
|
||||
else if (ich9_detected)
|
||||
return ich_spi_command(writecnt, readcnt, writearr, readarr);
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
|
|
@ -357,6 +360,8 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf)
|
|||
{
|
||||
if (it8716f_flashport)
|
||||
return it8716f_spi_chip_read(flash, buf);
|
||||
else if (ich7_detected)
|
||||
return ich_spi_read(flash, buf);
|
||||
else if (ich9_detected)
|
||||
return ich_spi_read(flash, buf);
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
|
|
@ -367,6 +372,8 @@ int spi_chip_write(struct flashchip *flash, uint8_t *buf)
|
|||
{
|
||||
if (it8716f_flashport)
|
||||
return it8716f_spi_chip_write(flash, buf);
|
||||
else if (ich7_detected)
|
||||
return ich_spi_write(flash, buf);
|
||||
else if (ich9_detected)
|
||||
return ich_spi_write(flash, buf);
|
||||
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
|
||||
|
|
|
|||
Loading…
Reference in New Issue