mb/google/octopus: Create Casta variant

This commit create a casta variant for Octopus. The initial settings
override the baseboard GPIO configuration for Touchscreen, LTE, Pen and
Trace modules.

BUG=b:119056117
BRANCH=None
TEST=None

Change-Id: I5d3f7df66981d84fb47a6aa248480ef53dfd90d0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/29763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/octopus/Kconfig

@@ -54,6 +54,7 @@ config VARIANT_DIR
 	default "bobba" if BOARD_GOOGLE_BOBBA
 	default "meep" if BOARD_GOOGLE_MEEP
 	default "ampton" if BOARD_GOOGLE_AMPTON
+	default "casta" if BOARD_GOOGLE_CASTA
 	default "octopus" if BOARD_GOOGLE_OCTOPUS
 
 config DEVICETREE
@@ -73,6 +74,7 @@ config MAINBOARD_PART_NUMBER
 	default "Bobba" if BOARD_GOOGLE_BOBBA
 	default "Meep" if BOARD_GOOGLE_MEEP
 	default "Ampton" if BOARD_GOOGLE_AMPTON
+	default "Casta" if BOARD_GOOGLE_CASTA
 	default "Octopus" if BOARD_GOOGLE_OCTOPUS
 
 config MAINBOARD_FAMILY
@@ -89,6 +91,7 @@ config GBB_HWID
 	default "BOBBA TEST 4516" if BOARD_GOOGLE_BOBBA
 	default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP
 	default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON
+	default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA
 	default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS
 
 config MAX_CPUS
@@ -119,11 +122,13 @@ config DRAM_PART_NUM_IN_CBI
 	default y if BOARD_GOOGLE_AMPTON
 	default y if BOARD_GOOGLE_FLEEX
 	default y if BOARD_GOOGLE_BOBBA
+	default y if BOARD_GOOGLE_CASTA
 
 config DRAM_PART_NUM_ALWAYS_IN_CBI
 	bool
 	depends on DRAM_PART_NUM_IN_CBI
 	default y if BOARD_GOOGLE_AMPTON
+	default y if BOARD_GOOGLE_CASTA
 
 config DRAM_PART_IN_CBI_BOARD_ID_MIN
 	int

src/mainboard/google/octopus/Kconfig.name

@@ -46,3 +46,9 @@ config BOARD_GOOGLE_AMPTON
 	select BASEBOARD_OCTOPUS_LAPTOP
 	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
 	select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
+
+config BOARD_GOOGLE_CASTA
+	bool "->  Casta"
+	select BASEBOARD_OCTOPUS_LAPTOP
+	select BOARD_GOOGLE_BASEBOARD_OCTOPUS
+	select NHLT_DA7219 if INCLUDE_NHLT_BLOBS

src/mainboard/google/octopus/variants/casta/Makefile.inc

@@ -0,0 +1,3 @@
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c

src/mainboard/google/octopus/variants/casta/gpio.c

@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config default_override_table[] = {
+	PAD_NC(GPIO_50, UP_20K), /* PCH_I2C_PEN_SDA -- unused */
+	PAD_NC(GPIO_51, UP_20K), /* PCH_I2C_PEN_SCL -- unused */
+	PAD_NC(GPIO_52, UP_20K), /* PCH_I2C_P_SENSOR_SDA -- unused */
+	PAD_NC(GPIO_53, UP_20K), /* PCH_I2C_P_SENSOR_SCL -- unused */
+
+	PAD_NC(GPIO_67, UP_20K), /* EN_PP3300_DX_LTE_SOC -- unused */
+
+	PAD_NC(GPIO_105, DN_20K), /* TOUCHSCREEN_RST -- unused */
+	PAD_NC(GPIO_108, NONE), /* PMU_SUSCLK -- unused */
+
+	PAD_NC(GPIO_114, DN_20K), /* I2C7 Touchscreen -- unused */
+	PAD_NC(GPIO_115, DN_20K), /* I2C7 Touchscreen -- unused */
+
+	PAD_NC(GPIO_117, UP_20K), /* PCIE_WAKE1_B - No LTE*/
+	PAD_NC(GPIO_119, UP_20K), /* PCIE_WAKE3_B - only use CNVI */
+
+	/* PCIE_CLKREQ3_B -- unused */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),
+	/* CAM_SOC_EC_SYNC */
+	PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
+			     DISPUPD),
+
+	PAD_NC(GPIO_138, UP_20K), /* PEN_PDCT_ODL -- unused */
+	PAD_NC(GPIO_139, UP_20K), /* PEN_INT_ODL -- unused */
+	PAD_NC(GPIO_140, UP_20K), /* PEN_RESET -- unused */
+
+	PAD_NC(GPIO_143, UP_20K), /* LTE_SAR_ODL -- unused */
+	PAD_NC(GPIO_144, UP_20K), /* PEN_EJECT(wake) -- unused */
+	PAD_NC(GPIO_145, UP_20K), /* PEN_EJECT(notification) -- unused */
+
+	PAD_NC(GPIO_161, UP_20K), /* LTE_OFF_ODL -- unused */
+	PAD_NC(GPIO_164, UP_20K), /* WLAN_PE_RST -- unused */
+
+	PAD_NC(GPIO_212, UP_20K), /* TOUCHSCREEN_INT_ODL -- unused */
+	PAD_NC(GPIO_213, UP_20K), /* EN_PP3300_TOUCHSCREEN -- unused */
+	PAD_NC(GPIO_214, UP_20K), /* P_SENSOR_INT_L -- unused */
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(default_override_table);
+	return default_override_table;
+}

src/mainboard/google/octopus/variants/casta/include/variant/acpi/dptf.asl

@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>

src/mainboard/google/octopus/variants/casta/include/variant/ec.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif

src/mainboard/google/octopus/variants/casta/include/variant/gpio.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */

src/mainboard/google/octopus/variants/casta/overridetree.cb

@@ -0,0 +1,50 @@
+chip soc/intel/apollolake
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+	}"
+
+	device domain 0 on
+		device pci 17.1 on
+			chip drivers/i2c/da7219
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
+				register "btn_cfg" = "50"
+				register "mic_det_thr" = "500"
+				register "jack_ins_deb" = "20"
+				register "jack_det_rate" = ""32ms_64ms""
+				register "jack_rem_deb" = "1"
+				register "a_d_btn_thr" = "0xa"
+				register "d_b_btn_thr" = "0x16"
+				register "b_c_btn_thr" = "0x21"
+				register "c_mic_btn_thr" = "0x3e"
+				register "btn_avg" = "4"
+				register "adc_1bit_rpt" = "1"
+				register "micbias_lvl" = "2600"
+				register "mic_amp_in_sel" = ""diff""
+				device i2c 1a on end
+			end
+		end	# - I2C 5
+		device pci 17.2 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
+				register "wake" = "GPE0_DW3_27"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end	# - I2C 6
+	end
+end