mb/google/octopus: Create Casta variant
This commit create a casta variant for Octopus. The initial settings override the baseboard GPIO configuration for Touchscreen, LTE, Pen and Trace modules. BUG=b:119056117 BRANCH=None TEST=None Change-Id: I5d3f7df66981d84fb47a6aa248480ef53dfd90d0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/29763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -54,6 +54,7 @@ config VARIANT_DIR
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default "bobba" if BOARD_GOOGLE_BOBBA
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default "meep" if BOARD_GOOGLE_MEEP
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default "ampton" if BOARD_GOOGLE_AMPTON
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default "casta" if BOARD_GOOGLE_CASTA
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default "octopus" if BOARD_GOOGLE_OCTOPUS
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config DEVICETREE
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@ -73,6 +74,7 @@ config MAINBOARD_PART_NUMBER
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default "Bobba" if BOARD_GOOGLE_BOBBA
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default "Meep" if BOARD_GOOGLE_MEEP
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default "Ampton" if BOARD_GOOGLE_AMPTON
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default "Casta" if BOARD_GOOGLE_CASTA
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default "Octopus" if BOARD_GOOGLE_OCTOPUS
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config MAINBOARD_FAMILY
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@ -89,6 +91,7 @@ config GBB_HWID
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default "BOBBA TEST 4516" if BOARD_GOOGLE_BOBBA
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default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP
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default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON
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default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA
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default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS
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config MAX_CPUS
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@ -119,11 +122,13 @@ config DRAM_PART_NUM_IN_CBI
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default y if BOARD_GOOGLE_AMPTON
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default y if BOARD_GOOGLE_FLEEX
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default y if BOARD_GOOGLE_BOBBA
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default y if BOARD_GOOGLE_CASTA
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config DRAM_PART_NUM_ALWAYS_IN_CBI
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bool
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depends on DRAM_PART_NUM_IN_CBI
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default y if BOARD_GOOGLE_AMPTON
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default y if BOARD_GOOGLE_CASTA
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config DRAM_PART_IN_CBI_BOARD_ID_MIN
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int
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@ -46,3 +46,9 @@ config BOARD_GOOGLE_AMPTON
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select BASEBOARD_OCTOPUS_LAPTOP
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select BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select NHLT_RT5682 if INCLUDE_NHLT_BLOBS
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config BOARD_GOOGLE_CASTA
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bool "-> Casta"
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select BASEBOARD_OCTOPUS_LAPTOP
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select BOARD_GOOGLE_BASEBOARD_OCTOPUS
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select NHLT_DA7219 if INCLUDE_NHLT_BLOBS
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@ -0,0 +1,3 @@
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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@ -0,0 +1,65 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <boardid.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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static const struct pad_config default_override_table[] = {
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PAD_NC(GPIO_50, UP_20K), /* PCH_I2C_PEN_SDA -- unused */
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PAD_NC(GPIO_51, UP_20K), /* PCH_I2C_PEN_SCL -- unused */
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PAD_NC(GPIO_52, UP_20K), /* PCH_I2C_P_SENSOR_SDA -- unused */
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PAD_NC(GPIO_53, UP_20K), /* PCH_I2C_P_SENSOR_SCL -- unused */
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PAD_NC(GPIO_67, UP_20K), /* EN_PP3300_DX_LTE_SOC -- unused */
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PAD_NC(GPIO_105, DN_20K), /* TOUCHSCREEN_RST -- unused */
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PAD_NC(GPIO_108, NONE), /* PMU_SUSCLK -- unused */
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PAD_NC(GPIO_114, DN_20K), /* I2C7 Touchscreen -- unused */
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PAD_NC(GPIO_115, DN_20K), /* I2C7 Touchscreen -- unused */
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PAD_NC(GPIO_117, UP_20K), /* PCIE_WAKE1_B - No LTE*/
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PAD_NC(GPIO_119, UP_20K), /* PCIE_WAKE3_B - only use CNVI */
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/* PCIE_CLKREQ3_B -- unused */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),
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/* CAM_SOC_EC_SYNC */
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PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
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DISPUPD),
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PAD_NC(GPIO_138, UP_20K), /* PEN_PDCT_ODL -- unused */
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PAD_NC(GPIO_139, UP_20K), /* PEN_INT_ODL -- unused */
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PAD_NC(GPIO_140, UP_20K), /* PEN_RESET -- unused */
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PAD_NC(GPIO_143, UP_20K), /* LTE_SAR_ODL -- unused */
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PAD_NC(GPIO_144, UP_20K), /* PEN_EJECT(wake) -- unused */
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PAD_NC(GPIO_145, UP_20K), /* PEN_EJECT(notification) -- unused */
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PAD_NC(GPIO_161, UP_20K), /* LTE_OFF_ODL -- unused */
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PAD_NC(GPIO_164, UP_20K), /* WLAN_PE_RST -- unused */
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PAD_NC(GPIO_212, UP_20K), /* TOUCHSCREEN_INT_ODL -- unused */
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PAD_NC(GPIO_213, UP_20K), /* EN_PP3300_TOUCHSCREEN -- unused */
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PAD_NC(GPIO_214, UP_20K), /* P_SENSOR_INT_L -- unused */
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};
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(default_override_table);
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return default_override_table;
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}
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_EC_H
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#define MAINBOARD_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <baseboard/gpio.h>
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#endif /* MAINBOARD_GPIO_H */
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@ -0,0 +1,50 @@
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chip soc/intel/apollolake
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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}"
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device domain 0 on
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device pci 17.1 on
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chip drivers/i2c/da7219
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
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register "btn_cfg" = "50"
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register "mic_det_thr" = "500"
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register "jack_ins_deb" = "20"
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register "jack_det_rate" = ""32ms_64ms""
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register "jack_rem_deb" = "1"
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register "a_d_btn_thr" = "0xa"
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register "d_b_btn_thr" = "0x16"
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register "b_c_btn_thr" = "0x21"
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register "c_mic_btn_thr" = "0x3e"
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register "btn_avg" = "4"
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register "adc_1bit_rpt" = "1"
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register "micbias_lvl" = "2600"
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register "mic_amp_in_sel" = ""diff""
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device i2c 1a on end
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end
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end # - I2C 5
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device pci 17.2 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)"
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register "wake" = "GPE0_DW3_27"
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register "probed" = "1"
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device i2c 15 on end
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end
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end # - I2C 6
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end
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end
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