nb/intel/sandybridge: Clarify register write

It is necessary to program this register before doing an I/O reset.

Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/sandybridge/raminit_common.c

@@ -1954,6 +1954,7 @@ static int jedec_write_leveling(ramctr_timing *ctrl)
 		write_mrreg(ctrl, channel, slotrank, 1,
 				make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7);
 
+	/* Needs to be programmed before I/O reset below */
 	const union gdcr_training_mod_reg training_mod = {
 		.write_leveling_mode = 1,
 		.enable_dqs_wl       = 5,