rockchip: rk3399: support basic clock driver
This patch initialize the PLL clocks and add function to
configure cpu freq. Right now, we set the little cpu freq to 600MHz.
In coreboot, we currently care about these four PLLs,
o. APLL for cpu clk, where A stands for AXI,
o. CPLL and GPLL are the generic PLL mainly for peripheral clk,
o. PPLL is only PMU clk.
For the peripheral clocks, there are thress clocks named as,
aclk_perihp,
aclk_perilp0,
hclk_perilp1,
where the 'h' and 'l' letters refer to High and Low speed.
As the diagram below, the aclk_perihp always be the parent of
more higher speed peripheral devices like pcie, and
hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto.
These three clocks can choose parent from GPLL or CPLL freely,
in this patch, they are all sourced from GPLL.
GPLL(594M)/CPLL(384M) APLL(600M for little core)
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`-- aclk_perihp `-- clk_core(600M == APLL)
| | |
| `-- periph_aclk(148.5M) `-- atclk_core(300M)
| `-- periph_hclk(148.5M) `-- aclkm_core(300M)
| `-- periph_pclk(37.125M) `-- pclk_dbg_core(100M)
|
`-- hclk_perilp1
| |
| `-- periph_hclk(99M) PPLL(594M)
| `-- periph_pclk(49.5M) |
| `-- pmu_pclk(99M)
`-- aclk_perilp0
|
`-- periph_aclk(99M)
`-- periph_hclk(99M)
`-- periph_pclk(49.5M)
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c
Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332386
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Lin Huang
Patrick Georgi
parent
b38895ea38
commit
a1f82a3498
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@ -11,15 +11,13 @@
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <arch/io.h>
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#include <arch/mmu.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <symbols.h>
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#include <soc/clock.h>
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void bootblock_soc_init(void)
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{
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rkclk_init();
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rkclk_configure_cpu(APLL_L_600_MHZ);
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}
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@ -11,11 +11,344 @@
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/grf.h>
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#include <soc/soc.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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struct pll_div {
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u32 refdiv;
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u32 fbdiv;
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u32 postdiv1;
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u32 postdiv2;
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u32 frac;
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};
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
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_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
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OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " STRINGIFY(__LINE__))
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
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static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
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static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
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static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
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static const struct pll_div *apll_l_cfgs[] = {
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[APLL_L_1600_MHZ] = &apll_l_1600_cfg,
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[APLL_L_600_MHZ] = &apll_l_600_cfg,
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};
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enum {
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/* PLL_CON0 */
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PLL_FBDIV_MASK = 0xfff,
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PLL_FBDIV_SHIFT = 0,
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/* PLL_CON1 */
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PLL_POSTDIV2_MASK = 0x7,
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PLL_POSTDIV2_SHIFT = 12,
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PLL_POSTDIV1_MASK = 0x7,
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PLL_POSTDIV1_SHIFT = 8,
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PLL_REFDIV_MASK = 0x3f,
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PLL_REFDIV_SHIFT = 0,
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/* PLL_CON2 */
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PLL_LOCK_STATUS_MASK = 1,
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PLL_LOCK_STATUS_SHIFT = 31,
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PLL_FRACDIV_MASK = 0xffffff,
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PLL_FRACDIV_SHIFT = 0,
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/* PLL_CON3 */
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PLL_MODE_MASK = 3,
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PLL_MODE_SHIFT = 8,
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PLL_MODE_SLOW = 0,
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PLL_MODE_NORM,
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PLL_MODE_DEEP,
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PLL_DSMPD_MASK = 1,
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PLL_DSMPD_SHIFT = 3,
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PLL_INTEGER_MODE = 1,
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/* PMUCRU_CLKSEL_CON0 */
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PMU_PCLK_DIV_CON_MASK = 0x1f,
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PMU_PCLK_DIV_CON_SHIFT = 0,
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/* CLKSEL_CON0 */
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ACLKM_CORE_L_DIV_CON_MASK = 0x1f,
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ACLKM_CORE_L_DIV_CON_SHIFT = 8,
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CLK_CORE_L_PLL_SEL_MASK = 3,
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CLK_CORE_L_PLL_SEL_SHIFT = 6,
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CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
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CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
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CLK_CORE_L_PLL_SEL_DPLL = 0x10,
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CLK_CORE_L_PLL_SEL_GPLL = 0x11,
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CLK_CORE_L_DIV_MASK = 0x1f,
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CLK_CORE_L_DIV_SHIFT = 0,
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/* CLKSEL_CON1 */
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PCLK_DBG_L_DIV_MASK = 0x1f,
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PCLK_DBG_L_DIV_SHIFT = 0x8,
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ATCLK_CORE_L_DIV_MASK = 0x1f,
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ATCLK_CORE_L_DIV_SHIFT = 0,
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/* CLKSEL_CON14 */
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PCLK_PERIHP_DIV_CON_MASK = 0x7,
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PCLK_PERIHP_DIV_CON_SHIFT = 12,
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HCLK_PERIHP_DIV_CON_MASK = 3,
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HCLK_PERIHP_DIV_CON_SHIFT = 8,
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ACLK_PERIHP_PLL_SEL_MASK = 1,
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ACLK_PERIHP_PLL_SEL_SHIFT = 7,
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ACLK_PERIHP_PLL_SEL_CPLL = 0,
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ACLK_PERIHP_PLL_SEL_GPLL = 1,
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ACLK_PERIHP_DIV_CON_MASK = 0x1f,
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ACLK_PERIHP_DIV_CON_SHIFT = 0,
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/* CLKSEL_CON23 */
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PCLK_PERILP0_DIV_CON_MASK = 0x7,
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PCLK_PERILP0_DIV_CON_SHIFT = 12,
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HCLK_PERILP0_DIV_CON_MASK = 3,
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HCLK_PERILP0_DIV_CON_SHIFT = 8,
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ACLK_PERILP0_PLL_SEL_MASK = 1,
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ACLK_PERILP0_PLL_SEL_SHIFT = 7,
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ACLK_PERILP0_PLL_SEL_CPLL = 0,
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ACLK_PERILP0_PLL_SEL_GPLL = 1,
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ACLK_PERILP0_DIV_CON_MASK = 0x1f,
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ACLK_PERILP0_DIV_CON_SHIFT = 0,
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/* CLKSEL_CON25 */
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PCLK_PERILP1_DIV_CON_MASK = 0x7,
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PCLK_PERILP1_DIV_CON_SHIFT = 8,
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HCLK_PERILP1_PLL_SEL_MASK = 1,
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HCLK_PERILP1_PLL_SEL_SHIFT = 7,
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HCLK_PERILP1_PLL_SEL_CPLL = 0,
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HCLK_PERILP1_PLL_SEL_GPLL = 1,
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HCLK_PERILP1_DIV_CON_MASK = 0x1f,
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HCLK_PERILP1_DIV_CON_SHIFT = 0,
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};
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#define VCO_MAX_KHZ (3200 * (MHz / KHz))
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#define VCO_MIN_KHZ (800 * (MHz / KHz))
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#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
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#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
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/* the div restrictions of pll in integer mode,
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* these are defined in * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
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*/
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#define PLL_DIV_MIN 16
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#define PLL_DIV_MAX 3200
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/* How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
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* Formulas also embedded within the Fractional PLL Verilog model:
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* If DSMPD = 1 (DSM is disabled, "integer mode")
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* FOUTVCO = FREF / REFDIV * FBDIV
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* FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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* Where:
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* FOUTVCO = Fractional PLL non-divided output frequency
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* FOUTPOSTDIV = Fractional PLL divided output frequency
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* (output of second post divider)
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* FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
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* REFDIV = Fractional PLL input reference clock divider
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* FBDIV = Integer value programmed into feedback divide
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*
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*/
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static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
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{
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/* All 8 PLLs have same VCO and output frequency range restrictions. */
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u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
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u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
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printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
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"postdiv2=%d, vco=%u khz, output=%u khz\n",
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pll_con, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_khz, output_khz);
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assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
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output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
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div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
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/* When power on or changing PLL setting,
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* we must force PLL into slow mode to ensure output stable clock.
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*/
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write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT,
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PLL_MODE_SLOW << PLL_MODE_SHIFT));
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/* use integer mode */
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write32(&pll_con[3],
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RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT,
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PLL_INTEGER_MODE << PLL_DSMPD_SHIFT));
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write32(&pll_con[0], RK_CLRSETBITS(PLL_FBDIV_MASK << PLL_FBDIV_SHIFT,
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div->fbdiv << PLL_FBDIV_SHIFT));
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write32(&pll_con[1],
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RK_CLRSETBITS(PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
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PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT |
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PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
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(div->postdiv2 << PLL_POSTDIV2_SHIFT) |
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(div->postdiv1 << PLL_POSTDIV1_SHIFT) |
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(div->refdiv << PLL_REFDIV_SHIFT)));
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/* waiting for pll lock */
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while (!(read32(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
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udelay(1);
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/* pll enter normal mode */
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write32(&pll_con[3], RK_CLRSETBITS(PLL_MODE_MASK << PLL_MODE_SHIFT,
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PLL_MODE_NORM << PLL_MODE_SHIFT));
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}
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void rkclk_init(void)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/* some cru registers changed by bootrom, we'd better reset them to
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* reset/default values described in TRM to avoid confusion in kernel.
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* Please consider these threee lines as a fix of bootrom bug.
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*/
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write32(&cru_ptr->clksel_con[12], 0xffff4101);
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write32(&cru_ptr->clksel_con[19], 0xffff033f);
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write32(&cru_ptr->clksel_con[56], 0x00030003);
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/* configure pmu pll(ppll) */
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rkclk_set_pll(&pmucru_ptr->ppll_con[0], &ppll_init_cfg);
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/* configure pmu pclk */
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pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
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assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f);
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write32(&pmucru_ptr->pmucru_clksel[0],
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RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT,
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pclk_div << PMU_PCLK_DIV_CON_SHIFT));
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/* configure gpll cpll */
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rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg);
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rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg);
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/* configure perihp aclk, hclk, pclk */
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aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
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assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
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PERIHP_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
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assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
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PERIHP_ACLK_HZ && (pclk_div < 0x7));
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write32(&cru_ptr->clksel_con[14],
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RK_CLRSETBITS(PCLK_PERIHP_DIV_CON_MASK <<
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PCLK_PERIHP_DIV_CON_SHIFT |
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HCLK_PERIHP_DIV_CON_MASK <<
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HCLK_PERIHP_DIV_CON_SHIFT |
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ACLK_PERIHP_PLL_SEL_MASK <<
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ACLK_PERIHP_PLL_SEL_SHIFT |
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ACLK_PERIHP_DIV_CON_MASK <<
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ACLK_PERIHP_DIV_CON_SHIFT,
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pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
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hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
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ACLK_PERIHP_PLL_SEL_GPLL <<
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ACLK_PERIHP_PLL_SEL_SHIFT |
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aclk_div << ACLK_PERIHP_DIV_CON_SHIFT));
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/* configure perilp0 aclk, hclk, pclk */
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aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
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assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
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PERILP0_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
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assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
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PERILP0_ACLK_HZ && (pclk_div < 0x7));
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write32(&cru_ptr->clksel_con[23],
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RK_CLRSETBITS(PCLK_PERILP0_DIV_CON_MASK <<
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PCLK_PERILP0_DIV_CON_SHIFT |
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HCLK_PERILP0_DIV_CON_MASK <<
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HCLK_PERILP0_DIV_CON_SHIFT |
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ACLK_PERILP0_PLL_SEL_MASK <<
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ACLK_PERILP0_PLL_SEL_SHIFT |
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ACLK_PERILP0_DIV_CON_MASK <<
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ACLK_PERILP0_DIV_CON_SHIFT,
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pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
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hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
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ACLK_PERILP0_PLL_SEL_GPLL <<
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ACLK_PERILP0_PLL_SEL_SHIFT |
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aclk_div << ACLK_PERILP0_DIV_CON_SHIFT));
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/* perilp1 hclk select gpll as source */
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hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
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assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
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GPLL_HZ && (hclk_div < 0x1f));
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pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
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assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
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PERILP1_HCLK_HZ && (hclk_div < 0x7));
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write32(&cru_ptr->clksel_con[25],
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RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK <<
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PCLK_PERILP1_DIV_CON_SHIFT |
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HCLK_PERILP1_DIV_CON_MASK <<
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HCLK_PERILP1_DIV_CON_SHIFT |
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HCLK_PERILP1_PLL_SEL_MASK <<
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HCLK_PERILP1_PLL_SEL_SHIFT,
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pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
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hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
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HCLK_PERILP1_PLL_SEL_GPLL <<
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HCLK_PERILP1_PLL_SEL_SHIFT));
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}
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void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq)
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{
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u32 aclkm_div;
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u32 pclk_dbg_div;
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u32 atclk_div;
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rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
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aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1;
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assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ &&
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aclkm_div < 0x1f);
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pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1;
|
||||
assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ &&
|
||||
pclk_dbg_div < 0x1f);
|
||||
|
||||
atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1;
|
||||
assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ &&
|
||||
atclk_div < 0x1f);
|
||||
|
||||
write32(&cru_ptr->clksel_con[0],
|
||||
RK_CLRSETBITS(ACLKM_CORE_L_DIV_CON_MASK <<
|
||||
ACLKM_CORE_L_DIV_CON_SHIFT |
|
||||
CLK_CORE_L_PLL_SEL_MASK <<
|
||||
CLK_CORE_L_PLL_SEL_SHIFT |
|
||||
CLK_CORE_L_DIV_MASK << CLK_CORE_L_DIV_SHIFT,
|
||||
aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
|
||||
CLK_CORE_L_PLL_SEL_ALPLL <<
|
||||
CLK_CORE_L_PLL_SEL_SHIFT |
|
||||
0 << CLK_CORE_L_DIV_SHIFT));
|
||||
|
||||
write32(&cru_ptr->clksel_con[1],
|
||||
RK_CLRSETBITS(PCLK_DBG_L_DIV_MASK << PCLK_DBG_L_DIV_SHIFT |
|
||||
ATCLK_CORE_L_DIV_MASK << ATCLK_CORE_L_DIV_SHIFT,
|
||||
pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
|
||||
atclk_div << ATCLK_CORE_L_DIV_SHIFT));
|
||||
}
|
||||
|
||||
void rkclk_configure_spi(unsigned int bus, unsigned int hz)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
|
||||
#define PMUGRF_BASE 0xff320000
|
||||
#define PMUSGRF_BASE 0xff330000
|
||||
#define PMUCRU_BASE 0xff750000
|
||||
#define CRU_BASE 0xff760000
|
||||
#define GRF_BASE 0xff770000
|
||||
#define TIMER0_BASE 0xff850000
|
||||
|
|
|
|||
|
|
@ -16,6 +16,91 @@
|
|||
#ifndef __SOC_ROCKCHIP_RK3399_CLOCK_H__
|
||||
#define __SOC_ROCKCHIP_RK3399_CLOCK_H__
|
||||
|
||||
void rkclk_configure_spi(unsigned int bus, unsigned int hz);
|
||||
#include <soc/addressmap.h>
|
||||
#include <types.h>
|
||||
|
||||
struct rk3399_pmucru_reg {
|
||||
u32 ppll_con[6];
|
||||
u32 reserved[0x1a];
|
||||
u32 pmucru_clksel[6];
|
||||
u32 pmucru_clkfrac_con[2];
|
||||
u32 reserved2[0x18];
|
||||
u32 pmucru_clkgate_con[3];
|
||||
u32 reserved3;
|
||||
u32 pmucru_softrst_con[2];
|
||||
u32 reserved4[2];
|
||||
u32 pmucru_rstnhold_con[2];
|
||||
u32 reserved5[2];
|
||||
u32 pmucru_gatedis_con[2];
|
||||
};
|
||||
check_member(rk3399_pmucru_reg, pmucru_gatedis_con[1], 0x134);
|
||||
|
||||
struct rk3399_cru_reg {
|
||||
u32 apll_l_con[6];
|
||||
u32 reserved[2];
|
||||
u32 apll_b_con[6];
|
||||
u32 reserved1[2];
|
||||
u32 dpll_con[6];
|
||||
u32 reserved2[2];
|
||||
u32 cpll_con[6];
|
||||
u32 reserved3[2];
|
||||
u32 gpll_con[6];
|
||||
u32 reserved4[2];
|
||||
u32 npll_con[6];
|
||||
u32 reserved5[2];
|
||||
u32 vpll_con[6];
|
||||
u32 reserved6[0x0a];
|
||||
u32 clksel_con[108];
|
||||
u32 reserved7[0x14];
|
||||
u32 clkgate_con[35];
|
||||
u32 reserved8[0x1d];
|
||||
u32 softrst_con[21];
|
||||
u32 reserved9[0x2b];
|
||||
u32 glb_srst_fst_value;
|
||||
u32 glb_srst_snd_value;
|
||||
u32 glb_cnt_th;
|
||||
u32 misc_con;
|
||||
u32 glb_rst_con;
|
||||
u32 glb_rst_st;
|
||||
u32 reserved10[0x1a];
|
||||
u32 sdmmc_con[2];
|
||||
u32 sdio0_con[2];
|
||||
u32 sdio1_con[2];
|
||||
};
|
||||
check_member(rk3399_cru_reg, sdio1_con[1], 0x594);
|
||||
|
||||
static struct rk3399_pmucru_reg * const pmucru_ptr = (void *)PMUCRU_BASE;
|
||||
static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE;
|
||||
|
||||
#define OSC_HZ (24*MHz)
|
||||
#define APLL_HZ (600*MHz)
|
||||
#define GPLL_HZ (594*MHz)
|
||||
#define CPLL_HZ (384*MHz)
|
||||
#define PPLL_HZ (594*MHz)
|
||||
|
||||
#define PMU_PCLK_HZ (99*MHz)
|
||||
|
||||
#define ACLKM_CORE_HZ (300*MHz)
|
||||
#define ATCLK_CORE_HZ (300*MHz)
|
||||
#define PCLK_DBG_HZ (100*MHz)
|
||||
|
||||
#define PERIHP_ACLK_HZ (148500*KHz)
|
||||
#define PERIHP_HCLK_HZ (148500*KHz)
|
||||
#define PERIHP_PCLK_HZ (37125*KHz)
|
||||
|
||||
#define PERILP0_ACLK_HZ (99000*KHz)
|
||||
#define PERILP0_HCLK_HZ (99000*KHz)
|
||||
#define PERILP0_PCLK_HZ (49500*KHz)
|
||||
|
||||
#define PERILP1_HCLK_HZ (99000*KHz)
|
||||
#define PERILP1_PCLK_HZ (49500*KHz)
|
||||
|
||||
enum apll_l_frequencies {
|
||||
APLL_L_1600_MHZ,
|
||||
APLL_L_600_MHZ,
|
||||
};
|
||||
|
||||
void rkclk_init(void);
|
||||
void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq);
|
||||
void rkclk_configure_spi(unsigned int bus, unsigned int hz);
|
||||
#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue