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mainboard/google/reef: set i2c bus timings by rise/fall times

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Provide the rise and fall times for the i2c buses and let the
library perform the necessary calculations for the i2c
controller registers instead of manually tuning the values.

BUG=chrome-os-partner:58889,chrome-os-partner:59565

Change-Id: I0c84658471d90309cdbb850e3128ae01780633af
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17397
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Aaron Durbin 2016-11-11 17:28:35 -06:00 committed by Martin Roth
parent 96831e69a0
commit a20e983236
1 changed files with 23 additions and 22 deletions
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45
src/mainboard/google/reef/variants/baseboard/devicetree.cb
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@ -71,39 +71,40 @@ chip soc/intel/apollolake
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Enable I2C2 bus early for TPM access and configure as 400kHz
# with manually tuned values.
# Enable I2C0 for audio codec at 400kHz
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
}"
# Enable I2C2 bus early for TPM at 400kHz
register "i2c[2]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 0xd0,
.scl_hcnt = 0x68,
.sda_hold = 0x27,
}
.rise_time_ns = 57,
.fall_time_ns = 28,
}"
# Limit trackpad speed to 400kHz with manually tuned values.
# touchscreen at 400kHz
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
}"
# trackpad at 400kHz
register "i2c[4]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 0xd0,
.scl_hcnt = 0x68,
.sda_hold = 0x27,
}
.rise_time_ns = 114,
.fall_time_ns = 164,
}"
# Limit digitizer speed to 400kHz with manually tuned values.
# digitizer at 400kHz
register "i2c[5]" = "{
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 0xd0,
.scl_hcnt = 0x68,
.sda_hold = 0x27,
}
.rise_time_ns = 152,
.fall_time_ns = 30,
}"
# Minimum SLP S3 assertion width 28ms.