sb/amd/sr5650: Get rid of device_t
Change-Id: If03864d5e32dfc4a2e5e11a96a4df62699ca4392 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki
parent
f129aed5c2
commit
a211c1bf94
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@ -177,8 +177,8 @@ static void sr5690_set_resources(struct device *dev)
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if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
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uint32_t reg;
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device_t amd_ht_cfg_dev;
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device_t amd_addr_map_dev;
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struct device *amd_ht_cfg_dev;
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struct device *amd_addr_map_dev;
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resource_t res_base;
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resource_t res_end;
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uint32_t base;
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@ -46,9 +46,9 @@ PCIE_CFG AtiPcieCfg = {
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0 /* GppPwr */
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};
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static void ValidatePortEn(device_t nb_dev);
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static void ValidatePortEn(struct device *nb_dev);
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static void ValidatePortEn(device_t nb_dev)
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static void ValidatePortEn(struct device *nb_dev)
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{
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}
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@ -56,7 +56,7 @@ static void ValidatePortEn(device_t nb_dev)
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* Compliant with CIM_33's PCIEPowerOffGppPorts
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* Power off unused GPP lines
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*****************************************************************/
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static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
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static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port)
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{
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printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port);
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u32 reg;
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@ -124,7 +124,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
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/**********************************************************************
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**********************************************************************/
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static void switching_gpp1_configurations(device_t nb_dev, device_t sb_dev)
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static void switching_gpp1_configurations(struct device *nb_dev, struct device *sb_dev)
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{
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u32 reg;
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struct southbridge_amd_sr5650_config *cfg =
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@ -165,7 +165,7 @@ static void switching_gpp1_configurations(device_t nb_dev, device_t sb_dev)
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/**********************************************************************
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**********************************************************************/
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static void switching_gpp2_configurations(device_t nb_dev, device_t sb_dev)
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static void switching_gpp2_configurations(struct device *nb_dev, struct device *sb_dev)
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{
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u32 reg;
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struct southbridge_amd_sr5650_config *cfg =
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@ -203,7 +203,7 @@ static void switching_gpp2_configurations(device_t nb_dev, device_t sb_dev)
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/* Follow the procedure for PCIE-GPP2 common initialization and
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* link training sequence. */
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}
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static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev)
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static void switching_gpp3a_configurations(struct device *nb_dev, struct device *sb_dev)
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{
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u32 reg;
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struct southbridge_amd_sr5650_config *cfg =
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@ -263,7 +263,7 @@ static void switching_gpp3a_configurations(device_t nb_dev, device_t sb_dev)
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* The sr5650 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
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* Space to a 256MB range within the first 4GB of addressable memory.
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*****************************************************************/
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void enable_pcie_bar3(device_t nb_dev)
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void enable_pcie_bar3(struct device *nb_dev)
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{
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printk(BIOS_DEBUG, "%s\n", __func__);
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set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
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@ -279,7 +279,7 @@ void enable_pcie_bar3(device_t nb_dev)
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* We should disable bar3 when we want to exit sr5650_enable, because bar3 will be
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* remapped in set_resource later.
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*****************************************************************/
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void disable_pcie_bar3(device_t nb_dev)
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void disable_pcie_bar3(struct device *nb_dev)
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{
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printk(BIOS_DEBUG, "%s\n", __func__);
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pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */
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@ -290,7 +290,7 @@ void disable_pcie_bar3(device_t nb_dev)
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/*
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* GEN2 Software Compliance
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*/
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void init_gen2(device_t nb_dev, device_t dev, u8 port)
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void init_gen2(struct device *nb_dev, struct device *dev, u8 port)
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{
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u32 reg, val;
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@ -358,7 +358,7 @@ const u8 pGpp111111[] = {0x0E, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E};
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* Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP3a Ports
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* PcieLibCplBufferAllocation
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*/
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static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev)
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static void gpp3a_cpl_buf_alloc(struct device *nb_dev, struct device *dev)
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{
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u8 dev_index;
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u8 *slave_cpl;
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@ -406,7 +406,7 @@ static void gpp3a_cpl_buf_alloc(device_t nb_dev, device_t dev)
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* Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP1/PCIE-GPP2 Ports
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* PcieLibCplBufferAllocation
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*/
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static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev)
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static void gpp12_cpl_buf_alloc(struct device *nb_dev, struct device *dev)
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{
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u8 gpp_cfg;
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u8 value;
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@ -442,14 +442,14 @@ static void gpp12_cpl_buf_alloc(device_t nb_dev, device_t dev)
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/*
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* Enable LCLK clock gating
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*/
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static void EnableLclkGating(device_t dev)
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static void EnableLclkGating(struct device *dev)
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{
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u8 port;
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u32 reg = 0;
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u32 mask = 0;
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u32 value = 0;
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device_t nb_dev = dev_find_slot(0, 0);
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device_t clk_f1= dev_find_slot(0, 1);
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struct device *nb_dev = dev_find_slot(0, 0);
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struct device *clk_f1= dev_find_slot(0, 1);
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reg = 0xE8;
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port = dev->path.pci.devfn >> 3;
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@ -502,7 +502,7 @@ static void EnableLclkGating(device_t dev)
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* port:
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* p2p bridge number, 4-10
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*****************************************/
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void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
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void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)
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{
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uint8_t training_ok = 1;
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@ -829,7 +829,7 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
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* Step 21: Register Locking
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* Lock HWInit Register of each pcie core
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*/
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static void lock_hwinitreg(device_t nb_dev)
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static void lock_hwinitreg(struct device *nb_dev)
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{
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/* Step 21: Register Locking, Lock HWInit Register */
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set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP1, 1 << 0, 1 << 0);
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@ -844,7 +844,7 @@ static void lock_hwinitreg(device_t nb_dev)
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*/
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void sr56x0_lock_hwinitreg(void)
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{
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device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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/* Lock HWInit Register */
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lock_hwinitreg(nb_dev);
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@ -859,7 +859,7 @@ void sr56x0_lock_hwinitreg(void)
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/*****************************************
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* Compliant with CIM_33's PCIEConfigureGPPCore
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*****************************************/
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void config_gpp_core(device_t nb_dev, device_t sb_dev)
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void config_gpp_core(struct device *nb_dev, struct device *sb_dev)
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{
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u32 reg;
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@ -886,7 +886,7 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
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/*****************************************
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* Compliant with CIM_33's PCIEMiscClkProg
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*****************************************/
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void pcie_config_misc_clk(device_t nb_dev)
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void pcie_config_misc_clk(struct device *nb_dev)
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{
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u32 reg;
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//struct bus pbus; /* fake bus for dev0 fun1 */
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@ -36,7 +36,7 @@ extern void set_pcie_dereset(void);
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extern void set_pcie_reset(void);
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struct resource * sr5650_retrieve_cpu_mmio_resource() {
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device_t domain;
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struct device *domain;
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struct resource *res;
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for (domain = all_devices; domain; domain = domain->next) {
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@ -51,7 +51,7 @@ struct resource * sr5650_retrieve_cpu_mmio_resource() {
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}
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/* extension registers */
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u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
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u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg)
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{
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/*get BAR3 base address for nbcfg0x1c */
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u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
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@ -62,7 +62,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
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return *((u32 *) addr);
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}
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void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
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void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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@ -81,42 +81,42 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
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}
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}
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u32 nbpcie_p_read_index(device_t dev, u32 index)
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u32 nbpcie_p_read_index(struct device *dev, u32 index)
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{
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return nb_read_index((dev), NBPCIE_INDEX, (index));
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}
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void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
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void nbpcie_p_write_index(struct device *dev, u32 index, u32 data)
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{
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nb_write_index((dev), NBPCIE_INDEX, (index), (data));
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}
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u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
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u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index)
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{
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return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
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}
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void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
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void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data)
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{
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nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
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}
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uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index)
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uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index)
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{
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return nb_read_index((nb_dev), L2CFG_INDEX, (index));
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}
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void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data)
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void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data)
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{
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nb_write_index((nb_dev), L2CFG_INDEX | (0x1 << 8), (index), (data));
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}
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uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index)
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uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index)
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{
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return nb_read_index((nb_dev), L1CFG_INDEX, (index));
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}
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void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data)
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void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data)
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{
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nb_write_index((nb_dev), L1CFG_INDEX | (0x1 << 31), (index), (data));
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}
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@ -130,8 +130,8 @@ void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data)
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void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
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{
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/* K8 Function1 is address map */
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device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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if (in_out) {
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u32 dword, sblk;
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@ -157,7 +157,7 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
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}
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}
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void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
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void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port)
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{
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switch (port) {
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case 2: /* GPP1, bit4-5 */
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@ -194,7 +194,7 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
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* 0: no device is present.
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* 1: device is present and is trained.
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********************************************************************************************************/
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u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port)
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{
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u16 count = 5000;
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u32 lc_state, reg, current_link_width, lane_mask;
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@ -300,7 +300,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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/*
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* Set Top Of Memory below and above 4G.
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*/
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void sr5650_set_tom(device_t nb_dev)
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void sr5650_set_tom(struct device *nb_dev)
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{
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msr_t sysmem;
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@ -315,12 +315,12 @@ void sr5650_set_tom(device_t nb_dev)
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htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
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}
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u32 get_vid_did(device_t dev)
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u32 get_vid_did(struct device *dev)
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{
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return pci_read_config32(dev, 0);
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}
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void detect_and_enable_iommu(device_t iommu_dev) {
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void detect_and_enable_iommu(struct device *iommu_dev) {
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uint32_t dword;
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uint8_t l1_target;
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unsigned char iommu;
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@ -332,7 +332,7 @@ void detect_and_enable_iommu(device_t iommu_dev) {
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if (iommu) {
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printk(BIOS_DEBUG, "Initializing IOMMU\n");
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device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (!nb_dev) {
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printk(BIOS_WARNING, "Unable to find SR5690 device! IOMMU NOT initialized\n");
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@ -496,7 +496,7 @@ void detect_and_enable_iommu(device_t iommu_dev) {
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}
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}
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void sr5650_iommu_read_resources(device_t dev)
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void sr5650_iommu_read_resources(struct device *dev)
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{
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unsigned char iommu;
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struct resource *res;
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@ -521,7 +521,7 @@ void sr5650_iommu_read_resources(device_t dev)
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compact_resources(dev);
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}
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void sr5650_iommu_set_resources(device_t dev)
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void sr5650_iommu_set_resources(struct device *dev)
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{
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unsigned char iommu;
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struct resource *res;
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@ -549,12 +549,12 @@ void sr5650_iommu_set_resources(device_t dev)
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pci_dev_set_resources(dev);
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}
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void sr5650_iommu_enable_resources(device_t dev)
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void sr5650_iommu_enable_resources(struct device *dev)
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{
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detect_and_enable_iommu(dev);
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}
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void sr5650_nb_pci_table(device_t nb_dev)
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void sr5650_nb_pci_table(struct device *nb_dev)
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{ /* NBPOR_InitPOR function. */
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u8 temp8;
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u16 temp16;
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@ -609,9 +609,9 @@ void sr5650_nb_pci_table(device_t nb_dev)
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* case 0 will be called twice, one is by CPU in hypertransport.c line458,
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* the other is by sr5650.
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***********************************************/
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void sr5650_enable(device_t dev)
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void sr5650_enable(struct device *dev)
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{
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device_t nb_dev = 0, sb_dev = 0;
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struct device *nb_dev = NULL, *sb_dev = NULL;
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int dev_ind;
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struct southbridge_amd_sr5650_config *cfg;
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@ -823,14 +823,14 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current)
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{
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uint8_t *p;
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device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (!nb_dev) {
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printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
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"device! IVRS table not generated...\n");
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return (unsigned long)ivrs;
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}
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device_t iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2));
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struct device *iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2));
|
||||
if (!iommu_dev) {
|
||||
printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
|
||||
"IOMMU device! IVRS table not generated...\n");
|
||||
|
|
@ -890,7 +890,7 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current)
|
|||
return current;
|
||||
}
|
||||
|
||||
unsigned long southbridge_write_acpi_tables(device_t device,
|
||||
unsigned long southbridge_write_acpi_tables(struct device *device,
|
||||
unsigned long current,
|
||||
struct acpi_rsdp *rsdp)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue