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soc/qualcomm/sc7280: update intf timing parameter calcualtion for eDP 

Correct the interface timing parameter calculation for eDP interface
to avoid writing into the blanking region.

BUG=b:255870643
TEST=Validated on sc7280 Zombie development board

Change-Id: I069ca351d8c60d071debb23a5e48840701441977
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72743
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Vinod Polimera 2023-02-03 10:55:15 +05:30 committed by Felix Held
parent a63ea89c04
commit a21df14924
1 changed files with 8 additions and 6 deletions
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14
src/soc/qualcomm/sc7280/display/disp.c
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@ -28,13 +28,15 @@ void mdss_intf_tg_setup(struct edid *edid)
hsync_period = edid->mode.ha + edid->mode.hbl; hsync_period = edid->mode.ha + edid->mode.hbl;
vsync_period = edid->mode.va + edid->mode.vbl; vsync_period = edid->mode.va + edid->mode.vbl;
display_vstart = edid->mode.vbl * hsync_period + edid->mode.hbl; display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period +
display_vend = (vsync_period * hsync_period) - 1; edid->mode.hbl - edid->mode.hso;
display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - edid->mode.hso - 1;
hsync_ctl = (hsync_period << 16) | edid->mode.hspw; hsync_ctl = (hsync_period << 16) | edid->mode.hspw;
display_hctl = edid->mode.hbl | (hsync_period - 1) << 16; active_vstart = display_vstart;
active_vstart = edid->mode.vbl * hsync_period; active_vend = active_vstart + (edid->mode.va * hsync_period) - 1;
active_vend = display_vend; active_hctl = ((edid->mode.hbl - edid->mode.hso + edid->mode.ha - 1) << 16) |
active_hctl = display_hctl; (edid->mode.hbl - edid->mode.hso);
display_hctl = active_hctl;
write32(&mdp_intf->intf_active_v_start_f0, active_vstart); write32(&mdp_intf->intf_active_v_start_f0, active_vstart);
write32(&mdp_intf->intf_active_v_end_f0, active_vend); write32(&mdp_intf->intf_active_v_end_f0, active_vend);