mb/google/var/gimble4es: Add gpios to lock
Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216583542 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that gimble boots successfully to kernel. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If71ceb07a9894a0571a9983d008058598693986f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -27,11 +27,11 @@ static const struct pad_config override_gpio_table[] = {
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PAD_NC(GPP_A22, NONE),
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/* B3 : PROC_GP2 ==> NC */
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PAD_NC(GPP_B3, NONE),
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PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
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/* B5 : ISH_I2C0_SDA ==> NC */
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PAD_NC(GPP_B5, NONE),
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PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
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/* B6 : ISH_I2C0_SCL ==> NC */
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PAD_NC(GPP_B6, NONE),
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PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
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/* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
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/* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
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@ -43,17 +43,17 @@ static const struct pad_config override_gpio_table[] = {
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PAD_NC(GPP_C4, NONE),
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/* D3 : ISH_GP3 ==> NC */
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PAD_NC(GPP_D3, NONE),
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PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
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/* D5 : SRCCLKREQ0# ==> NC */
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PAD_NC(GPP_D5, NONE),
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/* D9 : ISH_SPI_CS# ==> NC */
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PAD_NC(GPP_D9, NONE),
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PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
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/* D15 : ISH_UART0_RTS# ==> NC */
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PAD_NC(GPP_D15, NONE),
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PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
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/* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */
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PAD_CFG_GPO(GPP_D16, 1, DEEP),
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PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
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/* D17 : UART1_RXD ==> NC */
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PAD_NC(GPP_D17, NONE),
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PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
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/* E0 : SATAXPCIE0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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@ -64,11 +64,11 @@ static const struct pad_config override_gpio_table[] = {
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/* E7 : PROC_GP1 ==> NC */
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PAD_NC(GPP_E7, NONE),
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/* E10 : THC0_SPI1_CS# ==> NC */
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PAD_NC(GPP_E10, NONE),
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PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
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/* E16 : RSVD_TP ==> NC */
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PAD_NC(GPP_E16, NONE),
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/* E17 : THC0_SPI1_INT# ==> NC */
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PAD_NC(GPP_E17, NONE),
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PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
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/* E18 : DDP1_CTRLCLK ==> NC */
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PAD_NC(GPP_E18, NONE),
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/* E20 : DDP2_CTRLCLK ==> NC */
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