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nb/intel/x4x: Use read32p() 

Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes Haouas 2022-12-03 13:27:54 +01:00 committed by Felix Held
parent 421f1ee294
commit a2389ef316
1 changed files with 1 additions and 1 deletions
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src/northbridge/intel/x4x/bootblock.c
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@ -21,7 +21,7 @@ static uint32_t encode_pciexbar_length(void)
void bootblock_early_northbridge_init(void) void bootblock_early_northbridge_init(void)
{ {
/* Disable LaGrande Technology (LT) */ /* Disable LaGrande Technology (LT) */
read32((void *)TPM_BASE_ADDRESS); read32p(TPM_BASE_ADDRESS);
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);