nb/intel/x4x: Use read32p()

Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/northbridge/intel/x4x/bootblock.c

@@ -21,7 +21,7 @@ static uint32_t encode_pciexbar_length(void)
 void bootblock_early_northbridge_init(void)
 {
 	/* Disable LaGrande Technology (LT) */
-	read32((void *)TPM_BASE_ADDRESS);
+	read32p(TPM_BASE_ADDRESS);
 
 	const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
 	pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);