From a23d76a8bcaff5fedc370a9850d953005f261202 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Mon, 27 Sep 2021 13:06:53 +0800 Subject: [PATCH] soc/mediatek: Add an overridable function for WDT clear status mtk_wdt_clr_status is different for MT8186 and MT8195, so we move this function to soc folder. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834 Reviewed-by: Rex-BC Chen Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/common/Kconfig | 5 ----- src/soc/mediatek/common/include/soc/wdt.h | 2 +- src/soc/mediatek/common/wdt.c | 5 +++-- src/soc/mediatek/mt8195/Kconfig | 1 - src/soc/mediatek/mt8195/Makefile.inc | 8 ++++---- src/soc/mediatek/mt8195/wdt.c | 12 ++++++++++++ 6 files changed, 20 insertions(+), 13 deletions(-) create mode 100644 src/soc/mediatek/mt8195/wdt.c diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 754c0da580..b581ffb85f 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -29,11 +29,6 @@ config MEMORY_TEST This option enables memory basic compare test to verify the DRAM read or write is as expected. -config CLEAR_WDT_MODE_REG - bool - help - Enable this option to clear WTD mode register explicitly. - config DPM_FOUR_CHANNEL bool default n diff --git a/src/soc/mediatek/common/include/soc/wdt.h b/src/soc/mediatek/common/include/soc/wdt.h index 5847d4953f..6b27beffc3 100644 --- a/src/soc/mediatek/common/include/soc/wdt.h +++ b/src/soc/mediatek/common/include/soc/wdt.h @@ -21,7 +21,6 @@ struct mtk_wdt_regs { /* WDT_MODE */ enum { MTK_WDT_MODE_KEY = 0x22000000, - MTK_WDT_CLR_STATUS = 0x230001FF, MTK_WDT_MODE_DUAL_MODE = 1 << 6, MTK_WDT_MODE_IRQ = 1 << 3, MTK_WDT_MODE_EXTEN = 1 << 2, @@ -40,5 +39,6 @@ enum { static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE; int mtk_wdt_init(void); +void mtk_wdt_clr_status(uint32_t wdt_sta); #endif /* SOC_MEDIATEK_COMMON_WDT_H */ diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 05bd27d277..b228e56a05 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -5,6 +5,8 @@ #include #include +__weak void mtk_wdt_clr_status(uint32_t wdt_sta) { /* do nothing */ } + int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -12,8 +14,7 @@ int mtk_wdt_init(void) /* Writing mode register will clear status register */ wdt_sta = read32(&mtk_wdt->wdt_status); - if (CONFIG(CLEAR_WDT_MODE_REG)) - write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); + mtk_wdt_clr_status(wdt_sta); printk(BIOS_INFO, "WDT: Last reset was "); if (wdt_sta & MTK_WDT_STA_HW_RST) { diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index df1b5d8b47..b96ccd85a8 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -9,7 +9,6 @@ config SOC_MEDIATEK_MT8195 select CACHE_MRC_SETTINGS select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON - select CLEAR_WDT_MODE_REG select DPM_FOUR_CHANNEL if SOC_MEDIATEK_MT8195 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index f99fa33e0b..c3628992f9 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -11,7 +11,7 @@ bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c bootblock-y += ../common/uart.c -bootblock-y += ../common/wdt.c +bootblock-y += ../common/wdt.c wdt.c verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c @@ -20,7 +20,7 @@ verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c -verstage-y += ../common/wdt.c +verstage-y += ../common/wdt.c wdt.c ramstage-y += apusys.c romstage-y += ../common/auxadc.c @@ -40,7 +40,7 @@ romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c -romstage-y += ../common/wdt.c +romstage-y += ../common/wdt.c wdt.c romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif_spi.c pmif_spi.c romstage-y += ../common/pmif_spmi.c pmif_spmi.c @@ -79,7 +79,7 @@ ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c ramstage-y += ../common/usb.c usb.c -ramstage-y += ../common/wdt.c +ramstage-y += ../common/wdt.c wdt.c BL31_MAKEARGS += PLAT=mt8195 diff --git a/src/soc/mediatek/mt8195/wdt.c b/src/soc/mediatek/mt8195/wdt.c new file mode 100644 index 0000000000..c000bf7494 --- /dev/null +++ b/src/soc/mediatek/mt8195/wdt.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define MTK_WDT_CLR_STATUS 0x230001FF + +void mtk_wdt_clr_status(uint32_t wdt_sta) +{ + write32(&mtk_wdt->wdt_mode, MTK_WDT_CLR_STATUS); +}