soc/amd/cezanne: add basic MCA support

Currently the MCA support for Cezanne only clears the MCA status
registers. The MCA error handling and BERT table generation will be
added in subsequent patches.

Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/cezanne/Makefile.inc

@@ -39,6 +39,7 @@ ramstage-y	+= data_fabric.c
 ramstage-y	+= fch.c
 ramstage-y	+= fsp_s_params.c
 ramstage-y	+= gpio.c
+ramstage-y	+= mca.c
 ramstage-y	+= reset.c
 ramstage-y	+= root_complex.c
 ramstage-y	+= uart.c

src/soc/amd/cezanne/cpu.c

@@ -59,6 +59,7 @@ void mp_init_cpus(struct bus *cpu_bus)
 
 static void zen_2_3_init(struct device *dev)
 {
+	check_mca();
 	setup_lapic();
 	set_cstate_io_addr();
 

src/soc/amd/cezanne/include/soc/cpu.h

@@ -5,4 +5,6 @@
 
 #define CEZANNE_A0_CPUID	0x00a50f00
 
+void check_mca(void);
+
 #endif /* AMD_CEZANNE_CPU_H */

src/soc/amd/cezanne/mca.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/msr.h>
+#include <soc/cpu.h>
+
+/* Check the Machine Check Architecture Extension registers */
+void check_mca(void)
+{
+	/* TODO: Implement MCAX register checking and BERT table generation. */
+
+	/* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are
+	   aliases, we can use either set of registers. */
+	mca_clear_status();
+}